dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 274

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Processing States
Fast interrupts are not nestable because fast interrupts are only available as level 2 interrupts—one level 2
interrupt cannot interrupt another level 2 interrupt.
9.3.3
Interrupt requests on a DSP56800E–based chip are generated by one of three sources: hardware sources
outside the core (peripherals, interrupt request signals), hardware sources within the core (illegal
instructions, data access exceptions, debug port exceptions), and software interrupt instructions.
Each interrupt source has at least one associated interrupt vector—the address to which program flow is
transferred when an interrupt occurs. Interrupt vectors are located in a block of memory called the interrupt
vector table. The interrupt source provides the location of the appropriate vector to the interrupt control
hardware.
Exact information on possible interrupt sources, and the size and location of the vector table, can be found
in the user’s manual for the particular DSP56800E–based device.
9.3.3.1
Interrupt and reset sources outside the core are unique to a chip’s particular configuration of peripherals
and so on. Consult the user’s manual for the particular DSP56800E–based device.
9.3.3.2
The hardware interrupt sources within the core include the following:
9-8
3. The first 5 instruction words in a fast interrupt service routine cannot contain an instruction
4. The instructions for the level 2 interrupt service routine are located directly in the interrupt
5. To prevent one level 2 fast interrupt from interrupting another, the status register’s I1 and
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that accesses program memory.
vector table unless a jump or branch transfers control out of the vector table. As a result, a
level 2 interrupt service routine typically occupies more than 2 program words in the
interrupt vector table.
I0 bits should not be explicitly changed during a fast interrupt service routine. A fast
interrupt handler can still be interrupted by a level 3 interrupt.
Illegal instruction interrupts
Hardware stack overflow interrupts
Misaligned data access interrupts
Debugging (Enhanced OnCE) interrupts
Interrupt Sources
– STOP, WAIT, DEBUGHLT
– DEBUGEV when programmed to halt the core
– SWI, SWI #n, SWILP, ALIGNSP
– REP, DO, DOSLC
External Hardware Interrupt Sources
Hardware Interrupt Sources Within the Core
DSP56800E Core Reference Manual
Freescale Semiconductor