dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 526

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

MACSU
Operation:
D + (S1 × S2) → D
Description: Multiply one signed 16-bit source operand by one unsigned 16-bit operand, and add the 32-bit frac-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
A-182
Before Execution
A2
B2
0
0
tional product to the destination (D). The order of the registers is important. The first source register
(S1) must contain the signed value, and the second source (S2) must contain the unsigned value to pro-
duce correct fractional results. The fractional product is first sign extended before the 36-bit addition
is performed. If the destination is one of the 16-bit registers, only the high-order 16 bits of the fractional
result are stored. The result is not affected by the state of the saturation bit (SA). Note that for 16-bit
destinations, the sign bit may be lost for large fractional magnitudes.
In addition to single-precision multiplication of a signed-times-unsigned value and accumulation, this
instruction is used for multi-precision multiplications, as shown in Section 5.5, “Extended- and
Multi-Precision Operations,” on page 5-29.
MACSU
Prior to execution, the 16-bit Y1 register contains the (signed) negative value $FFF4, and the 16-bit
B1 register contains the (unsigned) positive value $0002. Execution of the MACSU instruction multi-
plies the 16-bit signed value in the Y1 register by the 16-bit unsigned value in B1 (yielding the frac-
tional product result of $FFFF:FFD0), then adds the sign extended result to the A accumulator, and
stores the signed result ($F:FFFF:FFF0) back into the A accumulator.
L
E
U
N
Z
V
LF
15
— Set if overflow has occurred in result
— Set if the extended portion of the result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Set if overflow has occurred in result
(S1 signed, S2 unsigned)
0000
0002
FFF4
P4
14
A1
B1
Y1
Multiply-Accumulate Signed × Unsigned
Y1,B1,A
13
P3
SR
P2
12
MR
DSP56800E Core Reference Manual
P1
11
0020
3456
0300
8000
A0
B0
Y0
P0
10
; multiply signed Y1 to unsigned B1 and
; accumulate in A
I1
9
Assembler Syntax:
MACSU
I0
8
SZ
7
After Execution
6
L
A2
B2
F
0
5
E
S1,S2,D
U
4
CCR
FFFF
FFF4
0002
A1
B1
Y1
N
3
SR
2
Z
Freescale Semiconductor
V
(no parallel move)
1
FFF0
3456
0318
8000
C
MACSU
0
A0
B0
Y0