dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 686

dsp56800e

Manufacturer Part Number

dsp56800e

Description

16-bit Digital Signal Controller Core

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.DSP56800E.pdf (706 pages)

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B-10

DEBUGHLT

Instruction

DEBUGEV

DECTSTA

CMPA.W

ILLEGAL

IMACUU

CMP.BP

IMACUS

IMPYSU

IMPYUU

DEC.BP

IMPY.W

CLR.BP

DECA.L

ENDDO

CMP.W

DOSLC

EOR.W

DEC.W

IMAC.L

IMPY.L

INC.BP

CLR.W

CMP.B

CMP.L

DEC.L

EOR.L

FRTID

INC.W

CLR.L

CMPA

DECA

JMPD

INC.L

CMP

JMP

DIV

Jcc

—

Restored from the FISR register

—

Table B-3. Condition Code Summary (Sheet 2 of 4)

*32

*xx

*32

*16

*32

*xx

—

*32

*xx

—

DSP56800E Core Reference Manual

*32

*16 *16 *16 *16 If the SA bit is set, if the first operand is not a register,

*24 *24 *24 *24

*16 *16 *16 *16

*32 *32 *32 *32

*24 *24 *24 *24

*32 *32

*16 *16

*32 *32 *32 *32

*xx

—

*16 *16

*xx

—

*32 *32 If the destination is a 16-bit register, the Z bit is set

*xx

—

*xx

—

— Affects LF and NL bits.

— Condition Codes are not affected by this instruction.

—

— Sets I1 and I0 bits in the SR.

—

— L is unchanged.

— See Section B.3.3.6, “IMPY.W,” for information on

—

based on the LSP of the result. Otherwise, the Z bit is

set based on the full 32-bit quantity.

and if the second operand is Y1, Y0, or X0, the U bit

is cleared if saturation occurs during the comparison.

Otherwise, the normal definition for the U bit is used.

V is set if the MSB of the destination operand is

changed as a result of the left shift; it is cleared other-

wise. V is not affected by SA or CM.

C is set if the MSB of the result is zero; it is cleared

otherwise.

See Section 9.3.2.2, “Fast Interrupt Processing,” on

page 9-6.

how the N bit is set.

Comments

Freescale Semiconductor

dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 686

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