dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 688

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dsp56800e

Manufacturer Part Number

dsp56800e

Description

16-bit Digital Signal Controller Core

Manufacturer

Freescale Semiconductor, Inc

Datasheet

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B-12

TSTDECA.W

Instruction

SXTA.W

TSTA.W

ZXTA.W

SUB.BP

SXTA.B

TST.BP

TSTA.B

TSTA.L

ZXTA.B

SUB.W

SWI #x

SWILP

TST.W

SUB.B

SUB.L

SWAP

SXT.B

SXT.L

TST.B

ZXT.B

RTSD

STOP

SUBA

TST.L

SUBL

TFRA

WAIT

RTS

SBC

SUB

SAT

SWI

TFR

TST

Tcc

SZ

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

*

*

*

*

VT

VT

VT

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

V

V

V

V

L

T

Table B-3. Condition Code Summary (Sheet 4 of 4)

*32

*36

*32

*xx

*36

*16

*xx

—

—

—

—

—

*8

*8

—

—

—

—

—

—

—

—

—

—

—

—

—

*8

—

—

—

—

—

—

—

—

—

—

—

—

E

*36

*32

*36

*32

*16

*xx

*xx

—

—

—

—

*8

*8

—

—

—

—

—

—

—

—

—

—

—

—

—

*8

—

—

—

—

—

—

—

—

—

—

—

—

—

U

DSP56800E Core Reference Manual

*36 *36 *36 *36

*32 *32 *32 *32

*36 *36

*32

*32 *32

*16 *16

*16 *16

*16 *16

*24 *24

*16 *16

*16 *16

*xx

*xx

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

*8

*8

*8

*8

*8

*8

N

*xx

*xx

—

—

—

—

*8

*8

—

—

—

—

—

—

—

—

—

—

—

—

—

*8

*8

*8

*8

—

—

—

—

Z

?

*xx

*xx

=0

=0

=0

=0

=0

=0

=0

=0

=0

=0

=0

=0

=0

—

—

—

—

*8

*8

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

V

*16 Condition codes based on test operation before the

*xx

*xx

=0 On a data ALU register.

=0 On a data ALU register.

=0 On a memory location.

=0 On a memory location.

=0 On a data ALU register. If the destination is a 16-bit

=0 On a memory location.

=0 On a data ALU accumulator (FF).

=0 On remaining data ALU registers.

=0 On a memory location.

=0

=0

=0

— Updates P4–P0 bits in SR.

— Updates P4–P0 bits in SR.

—

—

*8

*8

—

—

—

— Affects I1 and I0 bits in SR.

— Affects I1 and I0 bits in SR.

— Does not affect I1 and I0 bits in SR; no change.

—

—

—

—

—

— Only via parallel move.

—

—

—

—

—

C

register, the Z bit is set based on the LSP of the

result. Otherwise, the Z bit is set based on the full

32-bit quantity.

decrement occurs.

Comments

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