dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 298

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
Figure 10-8 on page 10-19 shows the fast interrupt pipeline for the case of a fast interrupt service routine
where the following occur:
Interrupt arbitration begins again in cycle #11. At this point, the level 3 interrupt is successfully arbitrated
and exception processing begins. However, the 2-cycle FRTID instruction (with 2 delay slots), which is
shown in the box in the ID stage of the pipeline, is a non-interruptible sequence. Since interrupts can only
occur when instructions complete execution, the pending level 3 interrupt must wait 1 cycle before
continuing into the exception processing state. This wait is indicated by the jagged arrow in Figure 10-8 on
page 10-19.
If 3 cycles were executed before the FRTID instruction (a case that is not shown in the figure), exception
processing would be delayed 2 cycles instead of the 1 cycle shown in the figure.
10-18
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•
Two cycles are executed before the FRTID instruction.
Simultaneously to this execution or a short time afterwards, a second interrupt at level 3 is received.
DSP56800E Core Reference Manual
Freescale Semiconductor