dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 518

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

LSRR.W
Operation:
D >> S →
S1 >> S2 → D
Description: This instruction can have two or three operands. Logically shift the source operand S1 or D to the right
Example 1:
Explanation of Example:
Example 2:
Explanation of Example:
A-174
Before Execution
Before Execution
A2
A2
F
0
D
by the value contained in the lowest 4 bits of either S2 or S, respectively (or by an immediate integer),
and store the result in the destination (D). The shift count can be a 4-bit positive integer, a value in a
16-bit register, or the MSP of an accumulator. For 36- and 32-bit destinations, only the MSP is shifted
and the LSP is cleared, with zero extension from bit 31 (the FF2 portion is ignored). The result is not
affected by the state of the saturation bit (SA).
LSRR.W Y1,Y0,A
Prior to execution, the Y1 register contains the value to be shifted ($AAAA), and the Y0 register con-
tains the amount by which to shift (least 4 bits of $FFF1 = 1). The contents of the destination register
are not important prior to execution because they have no effect on the calculated value. The LSRR.W
instruction logically shifts the value $AAAA by 1 bit to the right and places the result in the destination
register A (the LSP is cleared).
LSRR.W Y1,A
Prior to execution, A1 contains the value that is to be shifted ($AAAA), and the Y1 register contains
the amount by which to shift ($1). The LSRR.W instruction logically shifts the zero-extended value
$AAAA by 1 bit to the right and places the result in the destination register A (the LSP is cleared).
AAAA
AAAA
(no parallel move)
(no parallel move)
3456
0001
A1
Y1
A1
Y1
SR
SR
Multi-Bit Logical Right Shift Word
DSP56800E Core Reference Manual
FFF1
3456
0300
4567
000F
0300
A0
Y0
A0
Y0
; logical right shift of 16-bit Y1 by
; least 4 bits of Y0
; logical right shift of 16-bit A1 by
; least 4 bits of Y1
Assembler Syntax:
LSRR.W
LSRR.W
After Execution
After Execution
A2
A2
0
0
S,D
S1,S2,D
AAAA
5555
5555
0001
A1
Y1
A1
Y1
SR
SR
Freescale Semiconductor
(no parallel move)
(no parallel move)
FFF1
0000
0300
0000
000F
0300
LSRR.W
A0
Y0
A0
Y0