dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 409

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

BFSET
Operation:
1 → (<bitfield> of destination) (no parallel move)
Description: Test all selected bits of the destination operand. If all selected bits are set, C is set; otherwise, C is
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
cleared. Then set the selected bits, and store the result in the destination memory. A 16-bit immediate
value is used to specify which bits are tested and set. Those bits that are set in the immediate value are
the same bits that are tested and set in the destination; those bits that are cleared in the immediate value
are ignored in the destination. This instruction performs a read-modify-write operation on the destina-
tion memory location or register and requires two destination accesses.
This instruction is very useful in performing I/O and flag bit manipulation.
BFSET
Prior to execution, the 16-bit X memory location X:$5000 contains the value $3300. Execution of the
instruction tests the state of bits 10, 11, 14, and 15 in X:$5000, clears the C bit (because none of the
selected bits was set), and then sets the selected bits.
For destination operand SR:
For other destination operands:
L
C
If all bits in the mask are cleared, the instruction executes two NOPs and sets the C bit.
Before Execution
X:$5000
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
SR
P4
14
For this destination only, the C bit is not updated as is done for all other destination operands.
All SR bits except bits 14–10 are updated with values from the bitfield unit.
Bits 14–10 of the mask operand must be cleared.
Cleared if at least 1 bit specified by the mask is not set
#$CC00,X:$5000
13
P3
P2
12
3300
0301
MR
P1
11
Test Bitfield and Set
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
BFSET
BFSET
I0
8
; set bits in peripheral register
SZ
7
6
L
5
E
After Execution
X:$5000
#iiii,X:<ea>
#iiii,D
U
4
CCR
SR
N
3
2
Z
FF00
0300
V
(no parallel move)
(no parallel move)
1
C
0
BFSET
A-65