dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 581

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

NOTC
Operation:
D → D
Implementation Note:
Description: Take the one’s-complement of the destination operand (D), and store the result in the destination. This
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Instruction Fields:
Freescale Semiconductor
(no parallel move)
R2
This instruction is implemented by the assembler as an alias to the BFCHG instruction, with the 16-bit
immediate mask set to $FFFF. This instruction will dis-assemble as a BFCHG instruction.
instruction is a 16-bit operation. If the destination is a 36-bit accumulator, the one’s-complement is
performed on bits 31–16 of the accumulator. The remaining bits of the destination accumulator are not
affected. C is also modified as described in “Condition Codes Affected.”
NOTC
Prior to execution, the R2 register contains the value $555555. The execution of the instruction com-
plements the value in R2. C is modified as described in “Condition Codes Affected.”
L
C
The status register cannot be a destination operand for the NOTC instruction.
Refer to the section on the BFCHG instruction for legal operand and timing information.
Before Execution
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
SR
P4
14
Cleared if at least 1 bit specified by the mask is not set
R2
555555
13
P3
Logical Complement with Carry
P2
12
0301
MR
P1
11
P0
10
Instruction Set Details
; take the one’s-complement of R2
I1
9
Assembler Syntax:
NOTC
I0
8
SZ
7
6
L
R2
After Execution
5
E
D
U
4
CCR
SR
N
3
00AAAA
(no parallel move)
2
Z
0300
V
1
C
0
NOTC
A-237