dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 487

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

IMACUS
Operation:
D + (S1 × S2) → D
Description: Multiply one unsigned 16-bit source operand by one signed 16-bit operand, and add the 32-bit integer
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Instruction Opcodes:
Timing:
Memory:
Freescale Semiconductor
Operation
IMACUS q1.l,q2.h,Y
IMACUS
Before Execution
B2
A2
0
0
product to the destination (D). The order of the registers is important. The first source register (S1)
must contain the unsigned value, and the second source (S2) must contain the signed value to produce
the correct integer multiplication. The destination for this instruction is always the Y register. The re-
sult is not affected by the state of the saturation bit (SA).
This instruction is used to perform extended-precision multiplication calculations. It provides a meth-
od for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication
is performed, for example. See Section 5.5.3, “Multi-Precision Integer Multiplication,” on page 5-32
for an example that uses the IMACUS instruction.
IMACUS A0,B1,Y
Prior to execution, the A accumulator contains the value $0:FFFF:0002, the B accumulator contains
$0:FFFE:1234, and the 32-bit Y register contains $0000:0004. Execution of the IMACUS instruction
multiplies the 16-bit unsigned value in A0 by the 16-bit signed value in B1, adds the resulting 32-bit
product to the 32-bit Y register, and stores the result ($0000:0000) into Y.
The condition codes are not modified by this instruction.
1 oscillator clock cycle
1 program word
A0,C1,Y
A0,D1,Y
A0,A1,Y
A0,B1,Y
(S1 unsigned; S2 signed)
FFFE
FFFF
0000
B1
Y1
A1
Integer MAC Unsigned and Signed
Operands
; multiply unsigned A0 and signed B1,; add to Y
1234
0004
0002
C0,C1,Y
C0,D1,Y
B0,C1,Y
B0,D1,Y
B0
Y0
A0
15
0
Instruction Set Details
1
1
Assembler Syntax:
IMACUS
12
C
1
1
11
0
W
1
After Execution
0
B2
A2
Integer 16 × 16 multiply-accumulate:
F0 (unsigned) × F1 (signed)
0
0
1
S1,S2,D
0
8
FFFE
FFFF
0000
B1
Y1
A1
7
1
q
Comments
q
(no parallel move)
IMACUS
q
4
1234
0000
0002
B0
Y0
A0
0
3
1
1
A-143
1
0