dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 152

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Data Arithmetic Logic Unit
5.1.5
An arithmetic and logical shifter block performs shifting of data ALU registers by an immediate value or
by a value specified in a register. The unit is pipelined to maintain a throughput of one instruction per cycle
for 16-bit shifting (one instruction per two cycles for 32-bit shifting). The pipeline has two stages. Shifting
is performed in the first stage, and the second stage can add the result of the first stage to an accumulator in
the ALU unit. Shifting operations take two cycles to flow through the two pipeline stages (three cycles for
32-bit shifts). More information on the two-stage execution of the shifter unit appears in Section 10.2.2,
“Data ALU Execution Stages,” on page 10-4.
5.1.6
DSC algorithms can calculate values larger than the data precision of the machine when processing real
data streams. Normally a processor simply overflows such a result, but this treatment can create problems
for processing real-time signals. To eliminate the problems associated with overflow and underflow, the
DSP56800E provides the optional saturation of results using two limiters: the data limiter and the MAC
output limiter. The operation of the two limiter units is discussed in Section 5.8, “Saturation and Data
Limiting.”
5.2
The DSP56800E architecture provides four 36-bit accumulator registers for arithmetic operations. To
simplify the development of algorithms for signal processing and control, the DSP56800E provides three
methods for accessing the accumulators:
Accessing an entire accumulator (A, B, C, or D) is particularly useful for DSC tasks because it preserves
the full precision of multiplication and other ALU operations. Using the full accumulator also provides
limiting (or saturation) capability when storing the result of a computation would cause overflow; see
Section 5.8.1, “Data Limiter.”
Accessing 32-bit long values (A10, B10, C10, or D10) is important for control tasks and general-purpose
computing. It allows long variables to be written to memory and stored to other registers without
saturation.
The ability to access individual portions of an accumulator (FF2, FF1, or FF0) provides a great deal of
flexibility when systems and control algorithms are implemented. Saturation is always disabled when
portions of an accumulator are manipulated, allowing for the accurate manipulation of integer values. This
access method also allows for accumulators to be saved and restored without limiting, preserving the full
precision of a mathematical result. See Section 5.2.6, “Saving and Restoring Accumulators,” for more
information.
Note that while the individual accumulator register portions are normally accessible, C2, C0, D2, and D0
are exceptions. Refer to Section 5.2.2, “Accessing Portions of an Accumulator,” for details on how to
access these portions.
Table 5-1 on page 5-7 summarizes the various possible accesses. These are described in more detail in the
following sections.
5-6
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•
•
As an entire 36-bit register (FF)
As a 32-bit long register for store operations (FF10)
As individual component registers (FF2, FF1, or FF0)
Accessing the Accumulator Registers
Arithmetic and Logical Shifter
Data Limiter and MAC Output Limiter
DSP56800E Core Reference Manual
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