dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 44

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Core Architecture Overview
2.4.1
The DSP56800E core is composed of several independent functional units. The program controller,
address generation unit (AGU), and data arithmetic logic unit (ALU) contain their own register sets and
control logic, allowing them to operate independently and in parallel, which increases throughput. There is
also an independent bit-manipulation unit, which enables efficient bit-manipulation operations. Each
functional unit interfaces with the other units, memory, and the memory-mapped peripherals over the
core’s internal address and data buses. See Figure 2-4.
Instruction execution is pipelined to take advantage of the parallel units, significantly decreasing the
execution time for each instruction. For example, all within a single execution cycle, it is possible for the
data ALU to perform a multiplication operation, for the AGU to generate up to two addresses, and for the
program controller to prefetch the next instruction.
2-6
Core Block Diagram
Program Control Unit
HWS0
HWS1
FIRA
LA2
LA
Manipulation
PC
JTAG TAP
Enhanced
OnCE™
OMR
LC2
SR
LC
Unit
FISR
Bit-
Figure 2-4. DSP56800E Core Block Diagram
Instruction
Decoder
Interrupt
Looping
Unit
Unit
DSP56800E Core Reference Manual
DSP56800E Core
Y
A2
B2
C2
D2
MAC and ALU
Generation
Address
C1
D1
A1
B1
Y1
Y0
X0
(AGU)
M01
Unit
N3
Multi-Bit Shifter
Arithmetic
Logic Unit
(ALU)
Data
ALU1
A0
B0
C0
D0
R0
R1
N
SP
R2
R3
R4
R5
ALU2
Freescale Semiconductor
CDBW
CDBR
XDB2
XAB1
XAB2
PAB
PDB
Program
Interface
Interface
External
Memory
Memory
IP-BUS
Data
Bus