dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 107

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

4.2.1
The DSP56800E instruction set does not support logical operations using 16-bit immediate data. It is
possible to achieve the same result, however, using the bit-manipulation instructions. To simplify
implementing these operations, the DSP56800E assembler provides the following operations:
These operations are not new instructions, but aliases to existing bit-manipulation instructions. They are
mapped as indicated in Table 4-11.
Note that for the ANDC instruction, a one’s-complement of the mask value is used when remapping to the
BFCLR instruction. For the NOTC instruction, all bits in the 16-bit mask are set to one.
In Example 4-1, a logical OR operation is performed on an immediate value with a location in memory.
The assembler translates this instruction into
operation. If the assembled code is later dis-assembled, the instruction appears as a BFSET instruction.
4.2.2
The DSP56800E assembler performs a few additional mapping functions, either to allow an alternative
syntax for certain instructions or to simplify the addressing mode used by an instruction. These remapping
functions are discussed in the following sections.
4.2.2.1
Several instructions, such as the ADDA, SAT, and ZXT.B instructions, allow different source and
destination register operands to be specified. Often, however, the source and destination registers are the
same. For situations when they are the same, the DSP56800E assembler provides an alternate syntax in
which the operand is only specified once. Table 4-12 on page 4-12 lists the standard and duplicate-operand
syntaxes for these instructions.
Freescale Semiconductor
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ANDC—logically AND a 16-bit immediate value with a destination
EORC—logically exclusive OR a 16-bit immediate value with a destination
NOTC—take the logical one’s-complement of a 16-bit destination
ORC—logically OR a 16-bit immediate value with a destination
The ANDC, EORC, ORC, and NOTC Aliases
Instruction Operand Remapping
ORC
Duplicate Operand Remapping
Table 4-11. Aliases for Logical Instructions with Immediate Data
Instruction
Desired
EORC
ANDC
NOTC
ORC
Example 4-1. Logical OR with a Data Memory Location
#$00FF,X:$400; Set all bits of lower byte in X:$400
#xxxx,DST
#xxxx,DST
#xxxx,DST
Operands
Instruction Set Introduction
DST
BFSET #$00FF,X:$400
DSP56800E
Instruction
Remapped
BFCHG
BFCHG
BFCLR
BFSET
, which performs the same
#$FFFF,DST
#xxxx,DST
#xxxx,DST
#xxxx,DST
Operands
Instruction Aliases
4-11