dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 178

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Data Arithmetic Logic Unit
X:OP1UPR:X:OP1LWR × X:OP2UPR:X:OP2LWR
(Both 32-Bit Operands Are Signed)
; Unsigned x Unsigned Multiplication, save lower 16 bits of final result
; Signed x Unsigned Multiplication with Accumulation
; Unsigned x Signed Multiplication with Accumulation
; Lower 16 bits Correspond to Lower 32 bits of Final Result
; Upper 16 bits Correspond to Upper 32 bits of Final Result
; Correction for Fractional Result (C => RES2UPR:RES2LWR, D => RES1UPR:RES1LWR)
; Storing 64-bit Fractional Result in Memory
; ====> C2 may not be correct after the result is generated ...
This type of multiplication can also be performed as a 32 × 32 → 64-bit integer multiplication with a final
left shift of the result. Multi-precision integer multiplication is described in Section 5.5.3, “Multi-Precision
Integer Multiplication.”
5.5.3
Four provided instructions assist with multi-precision integer multiplications. When these instructions are
used, the multiplier accepts signed two’s-complement operands and unsigned two’s-complement operands.
Each instruction specifies not only which source operand is signed or unsigned, but also the location of the
16-bit operand (FF1 or FF0 portion of an accumulator):
5-32
•
•
IMACUU—multiply-accumulate with two unsigned operands
(first 16-bit operand located in FF0 portion, second in FF1)
IMACUS—multiply-accumulate with one unsigned and one signed operand
(unsigned 16-bit operand located in FF0 portion, signed in FF1)
MOVE.W
MOVE.W
MOVE.W
MOVE.W
IMPYUU
LSR16
IMPYSU
ADD
MOVE.L
IMACUS
ADD
ASL16
MOVE.W
ASR16
IMAC.L
SXT.L
ASL
ROL.L
MOVE.L D10,X:RES1
MOVE.L C10,X:RES2
Multi-Precision Integer Multiplication
Example 5-22. Multiplying Two Fractional Double-Precision Values
X:OP1UPR,A
X:OP1LWR,A0
X:OP2UPR,B
X:OP2LWR,B0
A0,B0,D
D,C
A1,B0,Y
Y,C
#0,Y
A0,B1,Y
Y,C
C,Y1
Y1,D1
C
A1,B1,C
D
D
C
DSP56800E Core Reference Manual
; Get first operand from memory
; Could use a MOVE.L to move 32-bit value to A
; Get first operand from memory
; Could use a MOVE.L to move 32-bit value to B
; Perform lower portion of multiplication
; Isolate upper 16 bits for accumulation
; LSP of D for RES1LWR
; Perform signed multiplication with upper 16 bits
; Accumulate result
; Perform signed multiplication with upper 16 bits
; Accumulate result
; Save lower 16 bits of result
; D has lower 32 bits of result
; MSP of D for RES1UPR
; Isolate upper 16 bits for accumulation
; Perform upper portion of multiplication
; Propagate bit 31 to EXT of D
; Corresponds to lower 32 bits of Final Fractional
; Result
; Corresponds to upper 32 bits of Final Fractional
; Result
; X:RES1UPR:RES1LWR = Lower 32 bits of Fractional
; Result
; X:RES2UPR:RES2LWR = Upper 32 bits of Fractional
; Result
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