dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 699

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
DEC.W instruction 4-3, 4-34, 4-48, A-117
DECA instruction 4-7, 4-41, A-120
DECA.L instruction 4-7, 4-41, A-121
DECTSTA instruction 4-6 to 4-7, 4-41, A-122
delay slots 4-13, 9-10, 10-9
delayed flow control instructions 4-12, 9-10
delayed instruction restrictions 4-14
digital signal processing 1-5
digital-to-analog conversion 1-5 to 1-6
DIV instruction 4-3, 4-34, A-123
division 5-21, A-123
DO instruction 2-9, 4-8, 4-14, 4-46, 8-11 to 8-12,
DO looping 8-7, A-126
DOSLC instruction 4-8, 4-14, 4-46, 8-18 to 8-19,
double-precision support 5-30 to 5-32
DSP56800 compatibility 1-1, 2-1
dual parallel reads 3-11 to 3-12, 4-49, 6-2
duplicate operand remapping 4-11
E
E, see extension in use bit (E)
ENDDO instruction 2-10, 4-8, 4-14, 4-47,
Enhanced OnCE, see Enhanced On-Chip Emulation
Enhanced On-Chip Emulation (Enhanced OnCE)
EOR.L instruction 4-6, 4-40, 4-48, A-134 to A-135
EOR.W instruction 4-6, 4-40, A-136
EORC instruction 4-6, 4-11, 4-14 to 4-15, 7-1, A-134,
even alignment 3-19, 6-8, 9-9, A-19, A-115, A-154,
EX, see external X memory bit (EX)
exception processing state 9-1 to 9-2, 11-6
exceptions 9-2 to 9-3
execution pipeline 10-1
extended-precision arithmetic
general-purpose 5-22
overflow 5-24
positive with remainder 5-23
signed 5-22 to 5-23
unsigned 5-23
without remainder 5-23
CMPA.W instruction A-110
condition code calculation 5-38, 8-7
DEBUGEV instruction A-111
DEBUGHLT instruction A-112
memory accesses 3-17
operations on unsigned values 5-28
TSTDECA.W instruction A-309
addition 5-29
8-18 to 8-19, A-126
A-130
A-132 to A-133
(Enhanced OnCE) module
module 1-2, 2-1, 9-9, 9-13, 11-1
A-138
A-191, A-228, A-274
Index
extension in use bit (E) 8-10
extension registers (A2, B2, C2, and D2) 3-2 to 3-3,
external X memory bit (EX) 8-6
F
fast Fourier transform (FFT) 8-10
fast interrupt processing 8-12, 8-14, 8-16, 9-6, 10-13
fast interrupt return address register (FIRA) 2-9, 8-4,
fast interrupt status register (FISR) 2-9, 8-4, 8-12
FIRA, see fast interrupt return address register (FIRA)
FISR, see fast interrupt status register (FISR)
forcing operators (<<, >>, <, and >) 3-26
four-quadrant division 5-21
fractional addition 5-16 to 5-17
fractional data types 3-5
fractional multiplication 5-18
FRTID instruction 4-9, 4-14, 4-45, 9-7, 10-13, A-139
H
hardware looping 2-9, 8-3, 8-7, 8-11 to 8-12, 8-17,
hardware stack 2-9, 8-3, 8-7, 8-11 to 8-12, 8-17, 8-19,
hardware stack register (HWS) 8-3 to 8-4, 8-12, 8-17
Harvard architecture, see memory architecture
high-level programming languages 1-1 to 1-2, 6-11,
HWS, see hardware stack register (HWS)
I
I0 and I1, see interrupt mask bits (I1 and I0)
ILLEGAL instruction 4-9, 4-47, 9-9, A-140
IMAC.L instruction 4-2, 4-28, A-141 to A-142
IMACUS instruction 4-2, 4-29, 5-28, 5-32, A-143
IMACUU instruction 4-2, 4-29, 5-32, A-144
IMPY.L instruction 4-2, 4-28, A-145
IMPY.W instruction 4-2, 4-28, A-147
IMPYSU instruction 4-2, 4-29, 5-28, 5-33, A-149
IMPYUU instruction 4-2, 4-30, 5-28, 5-33, A-150
INC.BP instruction 4-3, 4-34, A-152
INC.L instruction 4-3, 4-34, A-154
INC.W instruction 4-3, 4-35, 4-48, A-156
indexed address 3-33 to 3-37
instruction set summary 4-20
instructions
multiplication 4-29
subtraction 5-29
overflow 8-18, 9-12
underflow 8-3, 8-18
aliases 4-10
groups 4-1
5-4, 5-9, 8-6, 8-10
8-14
8-19, 8-22
9-9
8-16
Index-iii