dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 50

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Core Architecture Overview
2.5.3
A program bootstrap ROM is typically provided for devices that execute programs from on-chip RAM
instead of ROM. The bootstrap ROM is used to load the application into RAM on reset. The DSP56800E
architecture provides a bootstrapping mode, which fetches instructions from ROM and configures the
RAM as read-only. The operating mode register can then be reprogrammed to fetch instructions from
RAM. See the specific device’s user’s manual for information on bootstrapping mode.
2.5.4
An external bus interface extends the data and address buses off the chip, allowing access to external data
and program memory, I/O devices, or other peripherals. The external-bus-interface timing is
programmable, allowing for a wide variety of external devices. These devices can include slow memory
devices, other DSCs, MPUs in master/slave system configurations, or any number of other peripherals.
All three sets of buses (PAB and PDB; XAB1, CDBW, and CDBR; and XAB2 and XDB2) can be
extended to access external devices. Refer to the specific device’s user’s manual for information on
implementing the external bus interface.
2-12
Bootstrap Memory
External Bus Interface
DSP56800E Core Reference Manual
Freescale Semiconductor