dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 282

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
10.1
The eight stages of the pipeline, and their abbreviations, are as follows:
Table 10-1 on page 10-3 shows the relationship between fundamental operations, such as memory
accesses and calculations, and the various pipeline stages. The execution of data ALU operations in the
pipeline is discussed in more detail in Section 10.2.2, “Data ALU Execution Stages.”
10-2
1. Pre-Fetch 1 (P1)—The address of the instruction that is to be fetched is driven onto the
2. Pre-Fetch 2 (P2)—Program memory latches the instruction address and begins program
3. Instruction Fetch (IF)—Program memory places the instruction opcode onto the program
4. Instruction Decode (ID)—The instruction latch latches and decodes the opcode. It is at
5. Address Generation (AG)—The address generation unit (AGU) drives data memory
6. Operand Pre-Fetch 2 (OP2)—Data memory latches the data address and begins data
7. Execute and Operand Fetch (EX)—For a memory read, data memory places its value
8. Execute 2 (EX2)—Multiplications, MACs, and multi-bit shift instructions complete in this
program address bus (PAB).
memory access.
data bus (PDB).
this point in the pipeline that the instruction is identified.
access addresses onto the primary and secondary data address buses (XAB1 and XAB2).
Address and AGU calculations (including transfers done with the TFRA instruction) are
performed in the AGU’s arithmetic units and are stored in the destination AGU register.
memory access.
onto the primary and secondary data read buses (CDBR and XDB2), and the value or values
are captured in the move’s destination registers. For a memory write operation, data that is
to be written to data memory is placed onto the core data bus for writes (CDBW).
Multiplications and MACs begin in this stage in the data ALU’s arithmetic unit, and the
multiplication result is stored in an intermediate pipeline latch. Multi-bit shifting
instructions (arithmetic and logical) begin in this stage in the data ALU’s arithmetic unit,
and the temporary result is stored in an intermediate pipeline latch. All data ALU
calculations other than those that are previously listed are performed in the data ALU’s
arithmetic unit and are stored in the destination data ALU register, unless they are executed
using Late Execution.
stage in the data ALU’s arithmetic unit, and the final result is stored in the destination data
ALU register (ASLL.L, ASRR.L, and LSRR.L take an additional cycle since they are
2-cycle instructions). Data ALU calculations other than those that are listed previously are
performed in the data ALU’s arithmetic unit and are stored in the destination data ALU
register when they are executed using Late Execution.
Pipeline Stages
DSP56800E Core Reference Manual
Freescale Semiconductor