dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 276

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Processing States
9.3.3.3
The DSP56800E instruction set contains instructions that trigger an interrupt. Depending on the instruction
that is used, any priority interrupt can be generated. These instructions are commonly used for debugging
purposes or operating system calls.
9.3.3.3.1
The SWI instruction generates a non-maskable level 3 interrupt request. This request is serviced
immediately following the execution of the SWI instruction; no other instructions are ever executed
between the SWI instruction and the first instruction of the interrupt handler.
SWI’s ability to mask out lower-level interrupts makes it very useful for setting breakpoints in monitor
programs. The instruction can also be used for making a system call in a simple operating system.
9.3.3.3.2
The SWI #0, SWI #1, and SWI #2 instructions are maskable interrupt sources. Executing these instructions
generates an interrupt request at the specified priority level, and each typically has its own vector address.
These instructions execute in 1 clock cycle. If the interrupt requested by the SWI #x instruction is at a
priority level greater than or equal to the CCPL, the interrupt is recognized by the core. A minimum of 3
additional clock cycles are executed before the core forces three NOPs into the pipeline and executes the
first instruction located in the vector table. As a result, up to three instructions immediately after the
SWI #x instruction may be executed before the interrupt is serviced.
If the SWI #x instruction is executed with a priority level that is lower than the CCPL, the request is
latched as pending by the interrupt controller and will be serviced only after the core’s CCPL is lowered to
a level that is less than or equal to the priority of the instruction.
Note that the SWI #2 instruction can also be used for fast interrupt processing.
9.3.3.3.3
The operation of the SWILP instruction is very similar to the operation of the maskable SWI instructions.
Executing SWILP generates the lowest-priority interrupt request that is available.
This instruction executes in 1 clock cycle. If the CCPL is at level 0, the interrupt is recognized by the core.
In this case, a minimum of 3 additional clock cycles are executed before the core forces three NOPs into
the pipeline and executes the JSR located in the vector table. As a result, up to three instructions
immediately after the SWILP instruction may be executed before the interrupt is serviced.
If the SWILP instruction is executed when the CCPL is greater than level 0, the request is latched as
pending by the interrupt controller and will be serviced only after the core’s CCPL is lowered to level 0.
Processing SWILP, the lowest-priority interrupt, does not update the CCPL. It is possible for a level 0
interrupt request to interrupt the handler for SWILP.
This instruction is typically executed within other interrupt handlers, where its low priority will not be
recognized until all other interrupt handlers have completed execution. Used in this manner, the SWILP
instruction can schedule code for execution after all of the interrupt handlers have completed execution.
9.3.4
In general, interrupts can only occur between the execution of two instructions. However, there are certain
sequences of instructions that are not interruptible. When one of these sequences is executed, interrupts are
9-10
Non-Interruptible Instruction Sequences
Software Interrupt Instructions
SWI Instruction—Level 3
SWI #x Instructions—Levels 0–2
SWILP Instruction—Lowest Priority
DSP56800E Core Reference Manual
Freescale Semiconductor