dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 110

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Set Introduction
SWAP_LOOP
DONE
Similar strategies can be used on subroutines and interrupt handlers, where employing the RTSD and
RTID instructions can eliminate the wasted cycles associated with the RTS and RTI instructions.
4.3.2
Not all instructions are allowed in delay slots. The following instructions cannot be executed in a delay
slot. The assembler detects these instructions and flags them as illegal.
There are additional restrictions on instructions that are allowed in delay slots for the RTID instruction.
Because this instruction restores the value of the status register, instructions that update the status register
are not allowed. The assembler detects these cases, which appear in the following list, and flags them as
illegal.
In addition to all of the preceding restrictions, the instructions that can be in the delay slots for the FRTID
instruction are further limited. The assembler dis-allows the following:
4-14
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DO, DOSLC, REP, ENDDO
JMP, JMPD, Jcc, JSR, BRA, BRAD, Bcc, BSR, RTS, RTSD, RTI, RTID, FRTID
ADD.W with the following operands:
SWILP, SWI #0, SWI #1, SWI #2, SWI
STOP, WAIT
SWAP SHADOWS
Move instructions that access program memory
Any move clear or test instruction that accesses the SP, N3, M01, LA, LA2, LC, LC2, HWS, SR, or
OMR registers
The BFCHG, BFCLR, and BFSET instructions (and the aliases to them: ANDC, EORC, NOTC, and
ORC) that access the SP, N3, M01, LA, LA2, LC, LC2, HWS, SR, or OMR registers
The clear or test instructions (except TSTA.B, TSTA.W, TSTA.L, DECTSTA, or TSTDECA.W)
that access the SP,N3,M01,LA,LA2,LC,LC2, HWS, SR, or OMR registers
ALIGNSP
Tcc
DEBUGHLT, DEBUGEV
ADC, SBC, ROL.L, ROR.L, ROL.W, ROR.W
ADC, SBC, ROL.L, ROR.L, ROL.W, ROR.W
Any instruction in which the SP register is used as an address pointer, in an addressing mode, or in
an AGU calculation
Move instructions where the source or destination is the R0, R1, or N register
Delayed Instruction Restrictions
ADDA
CMPA
BLE
BRAD
MOVE.W
MOVE.W
...
#buflen-1,R0,R1
R0,R1
DONE
SWAP_LOOP
X:(R0)+,X0
X0,X:(R1)-
Example 4-3. Code Fragment with Delayed Branch
DSP56800E Core Reference Manual
ADD.W EEE,X:(SP-xx)
; put end of buffer in R1
; check if done yet
; if R0 >= R1, we’re done
; delayed branch to top of loop
; swap occurs in the delay slots!
; subsequent code...
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