dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 170

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Data Arithmetic Logic Unit
; Four-Quadrant Division of Signed Fractional Data (B1:B0 / X0)
; Generates signed quotient only, no remainder
; Setup
; Division
; Correct quotient
DONE
; Four-Quadrant Division of Signed Integer Data (B1:B0 / X0)
; Generates signed quotient only, no remainder
; Setup
; Division
; Correct quotient
DONE
5.3.4.4
Both integer and fractional division are subject to division overflow. Overflow occurs when the correct
value of the quotient does not fit into the destination available to store it. For the division of fractional
numbers, the result must be a 16-bit, signed, fractional value that satisfies the following equation:
When the magnitude of the dividend is larger than the magnitude of the divisor, this relation can never be
satisfied; the result is always larger in magnitude than 1.0. The dividend should be scaled to avoid this
condition.
Integer division can also overflow. Correct execution without overflow occurs only when the result of the
division fits within the range of a signed 16-bit word:
The numerator should be scaled if necessary to ensure this condition.
5-24
–1.0 ≤ quotient < +1.0 – 2
–2
–15
MOVE.W
ABS
EOR
BFCLR
REP
DIV
BGE
NEG
ASL
MOVE.W
ABS
EOR
BFCLR
REP
DIV
BGE
NEG
Division Overflow
≤ quotient ≤ [2
B,Y1
B
X0,Y1
#$0001,SR
16
X0,B
DONE
B
B
B,Y1
B
X0,Y1
#$0001,SR
16
X0,B
DONE
B
Example 5-17. Signed DIvision Without Remainder
15
– 1]
DSP56800E Core Reference Manual
–15
; Save Sign Bit of dividend (B1) in MSB of Y1
; Force dividend positive
; Save sign bit of quotient in N bit of SR
; Clear carry bit: required for 1st DIV instr
; Form positive quotient in B0
; If correct result is positive, then done
; Else negate to get correct negative result
; (At this point, the correctly signed
; quotient is in B0 but the remainder is not
; correct)
; Shift of dividend required for integer
; division
; Save Sign Bit of dividend (B1) in MSB of Y1
; Force dividend positive
; Save sign bit of quotient in N bit of SR
; Clear carry bit: required for 1st DIV instr
; Form positive quotient in B0
; If correct result is positive, then done
; Else negate to get correct negative result
; (At this point, the correctly signed
; quotient is in B0 but the remainder is not
; correct)
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