dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 508

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

LSL.W
Operation:
(see following figure)
Description: Logically shift 16 bits of the destination operand (D) by 1 bit to the left, and store the result in the des-
Example:
Explanation of Example:
Condition Codes Affected:
A-164
Before Execution
B2
6
tination. If the destination is a 36-bit accumulator, the result is stored in the MSP of the accumulator
(FF1 portion), and the remaining portions of the accumulator are not modified. The MSB of the desti-
nation (bit 31 if the destination is a 36-bit accumulator) prior to the execution of the instruction is shift-
ed into C, and zero is shifted into the LSB of D1 (bit 16 if the destination is a 36-bit accumulator). The
result is not affected by the state of the saturation bit (SA).
LSL.W
Prior to execution, the 36-bit B accumulator contains the value $6:C555:00AA. Execution of the
LSL.W instruction shifts the 16-bit value in the B1 register by 1 bit to the left and stores the result back
in the B1 register. The C bit is set because bit 31 of B1 was set prior to the execution of the instruction.
The N bit is also set because bit 31 of accumulator B is set. The overflow bit V is always cleared.
N
Z
V
C
LF
15
— Set if bit 31 of an accumulator result or bit 15 of a 16-bit register result is set
— Set if the MSP of result or all bits of a 16-register result are zero
— Always cleared
— Set if bit 31 of accumulator or bit 15 of a 16-bit register was set prior to the execution
C555
P4
14
B1
of the instruction
B
13
P3
C
SR
P2
12
MR
DSP56800E Core Reference Manual
Logical Shift Left Word
P1
11
Unch.
00AA
0302
D2
B0
P0
10
; multiply B1 by 2
I1
9
Assembler Syntax:
LSL.W
D1
I0
8
SZ
7
After Execution
6
L
B2
6
Unchanged
5
E
D
D0
U
4
CCR
8AAA
B1
N
3
(no parallel move)
SR
2
Z
Freescale Semiconductor
V
1
0
00AA
0309
C
0
B0
LSL.W