dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 42

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Core Architecture Overview
2.3
The DSP56800E has a dual Harvard architecture with separate program and data memory spaces, as shown
in Figure 2-2. This architecture allows for simultaneous program and data memory accesses. The data
memory interface also supports two simultaneous read operations, enabling up to three simultaneous
memory accesses.
The block of memory containing reset and interrupt vectors can be any size and can be located anywhere in
program memory. Peripheral registers are memory mapped into a 64-location region in the data memory
space.
A 64-word block of data memory allocated for memory-mapped IP-BUS peripheral registers can be
located anywhere in data memory. Usually the location of this memory block is chosen so that it does not
overlap with RAM or ROM data memory. The X:<<pp addressing mode (see Section 3.6.5.2, “I/O Short
Address: <<pp,” on page 3-43) provides efficient access to this memory range, enabling single-word,
single-cycle move and bit-manipulation instructions.
Note that the top 12 locations in the peripheral register area ($xxFFF4 through $xxFFFF) are reserved for
use by the DSP56800E core, interrupt priority functions, and bus control functions, as shown in Table 2-1
on page 2-3.
The compiler has access only to the lower 16 Mbyte of data memory.
2-4
$1FFFFF
Dual Harvard Memory Architecture
$0
15
Program
Interrupt
Memory
Vectors
Space
Figure 2-2. DSP56800E Dual Harvard Memory Architecture
0
2M (4 Mbyte)
0
DSP56800E Core Reference Manual
(Relocatable)
$FFFFFF
$xxFFFF
$xxFFC0
$0
15
Optimized for
Peripherals
Memory
IP-BUS
Space
Data
0
X:<<pp Addressing
Freescale Semiconductor
16M (32 Mbyte)
64K
(64K – 64)
0
Accessible with
(Relocatable)