dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 582
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dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 582 of 706
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OR.L
Operation:
S + D → D (no parallel move)
where + denotes the logical inclusive OR operator
Description: Perform a logical OR operation on the source operand (S) with the destination operand (D), and store
Description:
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
A-238
Operation
OR.L
Before Execution
B2
0
the result in the destination. This instruction is a 32-bit operation. The destination must be an accumu-
lator or the 32-bit Y register. The source can be any data ALU register. If the destination is a 36-bit
accumulator, the OR.L operation is performed on the source and bits 31–0 of the accumulator. The re-
maining bits of the destination accumulator are not affected. If the source is a 16-bit register, the OR.L
operation is performed on the source and bits 31–16 of the destination. The other bits of the destination
remain unchanged. The result is not affected by the state of the saturation bit (SA).
This instruction is used for the logical OR of two registers. If it is desired to perform an OR on a 16-bit
immediate value with a register or memory location, then the ORC instruction is appropriate.
OR.L
Prior to execution, the 16-bit Y register contains the value $FF0000FF, and the 36-bit B accumulator
contains the value $0:1234:5678. The OR.L Y,B instruction performs a logical OR on B10 and Y and
stores the result back into the B accumulator.
N
Z
V
LF
15
— Set if bit 31 of accumulator result or MSB of register result is set
— Set if bits 31–0 of accumulator result or all bits of register result are zero
— Always cleared
FF00
1234
P4
14
B1
Y1
Y,B
SR
13
P3
Operands
FFF,fff
P2
12
MR
Logical Inclusive OR Long
DSP56800E Core Reference Manual
P1
11
00FF
5678
0300
B0
Y0
P0
10
; OR Y with B
I1
9
C
1
Assembler Syntax:
OR.L
I0
8
W
1
SZ
7
32-bit logical OR
After Execution
6
L
B2
0
5
E
S,D
U
4
CCR
FF34
FF00
B1
Y1
N
3
(no parallel move)
SR
Comments
2
Z
Freescale Semiconductor
V
1
56FF
00FF
0308
C
0
B0
Y0
OR.L
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