dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 275

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

9.3.3.2.1
The illegal instruction interrupt is a non-maskable level 3 interrupt source. It is generated when the
DSP56800E core identifies an instruction as invalid. The illegal instruction interrupt is serviced
immediately following the attempted execution of an undefined operation code—that is, no other
instructions are executed between the illegal instruction and the first JSR instruction that is fetched from
the interrupt vector table in the exception processing state.
It is not possible to recover from an illegal instruction exception because critical state information is lost
when an invalid instruction is executed. However, handling this interrupt can be used for diagnostic
purposes—to locate the faulty code. The address of the instruction that immediately follows the illegal
instruction is pushed on the stack when the illegal instruction exception handler is entered. This address
can be used to locate the illegal instruction in memory.
The ILLEGAL instruction is a mnemonic for one of the invalid instruction opcodes. It can be used to test
the illegal instruction interrupt service routine.
Note that the illegal instruction exception is not necessarily generated for all invalid opcodes. Opcodes
with addressing modes that are not technically illegal, but that perform no useful work, might not generate
an exception even though these opcodes are not supported and thus are considered illegal.
9.3.3.2.2
The hardware stack overflow interrupt is a non-maskable level 3 interrupt source. Encountering the
hardware stack overflow interrupt request means that more than two values have been stacked onto the
hardware stack and that the oldest top-of-loop address has been lost (see Section 8.4, “Hardware Stack,” on
page 8-17). The hardware stack overflow interrupt is non-recoverable and is used primarily for debugging.
The hardware stack overflow refers only to the hardware stack and is not affected by the software stack
operation.
9.3.3.2.3
The misaligned data access interrupt is a non-maskable level 3 interrupt source. It occurs when a 32-bit
long-word value is accessed from data memory and the address that is used to access the data is
misaligned. A long-word value must be accessed from memory using an even word address, except when
SP is used in an indirect addressing mode. In the latter case, the value must be accessed using an odd word
address when it is accessed via the stack pointer register. If the long word is not aligned in this manner, a
misaligned data access interrupt is generated. See Section 3.5.3, “Accessing Long-Word Values Using
Word Pointers,” on page 3-19 for more information on the correct alignment for long-word values in
memory.
9.3.3.2.4
The Enhanced On-Chip Emulation module, which provides integrated debugging support for the
DSP56800E, is capable of generating interrupts. These interrupts provide the Enhanced OnCE module
with the capability of executing instructions. See Chapter 11, “JTAG and Enhanced On-Chip Emulation
(Enhanced OnCE),” for more information on the capabilities of the Enhanced OnCE module.
The Enhanced OnCE interrupts can be disabled or programmed to one of three different priority
levels—level 1 through level 3.
Freescale Semiconductor
Illegal Instruction Interrupt
Hardware Stack Overflow Interrupt
Misaligned Data Access Interrupt
Debugging (Enhanced OnCE) Interrupts
Processing States
Exception Processing State
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