dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 17

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 7-1
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 9-1
Figure 9-2
Figure 9-3
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
Figure 10-7
Figure 10-8
Figure 10-9
Figure 10-10 Interrupt Latency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
Figure 10-11 Interrupt Latency Calculation—Non-Interruptible Instructions . . . . . . . . . . . 10-23
Figure 10-12 Interrupt Latency and the REP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
Figure 10-13 Delay When Updating the CCPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 11-6
Figure 11-7
Freescale Semiconductor
Address Generation Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Dual Parallel Read Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Address Generation Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Word vs. Byte Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Executing the
Executing the
Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
37-Location Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Simple Five-Location Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Linear Addressing with a Modulo Modifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
Bit-Manipulation Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Program Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Program Controller Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Effects of the JSR Instruction on the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Example Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Example Data-Memory Execution Mode Memory Map . . . . . . . . . . . . . . . . . 8-24
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Control Flow in Normal Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Control Flow in Fast Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
DSP56800E Eight-Stage Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Standard Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Execution of the RTID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Interrupting an Interrupt Handler (Nested Interrupt) . . . . . . . . . . . . . . . . . . . 10-12
Fast Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Interrupting a Fast Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Interrupting After Completing the Fastest Fast Interrupt Routine . . . . . . . . . 10-17
Interruption by Level 3 Interrupt During FRTID Execution . . . . . . . . . . . . . 10-19
Second Interrupt Case with 4 Cycles Executed in FRTID Delay Slots . . . . . 10-21
DSP56800E On-Chip System with Debug Port . . . . . . . . . . . . . . . . . . . . . . . . 11-3
JTAG/Enhanced OnCE Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . 11-5
Breakpoint Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Trigger 1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Trigger 2 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Realtime Data Transfer Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Step Counter — Started upon Exiting Debug State . . . . . . . . . . . . . . . . . . . . 11-13
MOVE.L X:(R3+2),D
MOVEU.BP X:(R1+7),B
List of Figures
Instruction . . . . . . . . . . . . . . . . . . . . . . . 6-12
Instruction . . . . . . . . . . . . . . . . . . . . . 6-17
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