dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 45

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

The major components of the core are the following:
The following sections describe these components.
2.4.2
The core contains three address buses: the program memory address bus (PAB), the primary data address
bus (XAB1), and the secondary data address bus (XAB2). The program address bus is 21 bits wide and is
used to address (16-bit) words in program memory. The two 24-bit data address buses allow for two
simultaneous read accesses to data (X) memory. The XAB1 bus can address byte, word, and long data
types. The XAB2 bus is limited to (16-bit) word accesses.
All three buses address on-chip memory. They can also address off-chip memory on devices that contain
an external bus interface unit.
2.4.3
Data transfers inside the chip occur over the following buses:
Data transfers between the data ALU and data memory use the CDBR and CDBW when a single memory
read or write is performed. When two simultaneous memory reads are performed, the transfers use the
CDBR and XDB2 buses. All other data transfers to core blocks occur using the CDBR and CDBW buses.
Peripheral transfers occur through the IP-BUS interface. Instruction word fetches occur over the PDB.
This bus structure supports up to three simultaneous 16-bit transfers. Any one of the following can occur in
a single clock cycle:
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Address buses
Data buses
Data arithmetic logic unit (ALU)
Address generation unit (AGU)
Program controller
Bit-manipulation unit
Enhanced OnCE debugging module
Two uni-directional 32-bit buses:
— Core data bus for reads (CDBR)
— Core data bus for writes (CDBW)
Two uni-directional 16-bit buses:
— Secondary X data bus (XDB2)
— Program data bus (PDB)
IP-BUS interface
One instruction fetch
One read from data memory
One write to data memory
Two reads from data memory
One instruction fetch and one read from data memory
Address Buses
Data Buses
Core Architecture Overview
System Architecture and Peripheral Interface
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