dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 111

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

4.3.3
Instructions that are executed in delay slots are not interruptible. From the time that execution begins for a
delayed instruction to the end of execution for the instruction that occupies the last delay slot, no interrupts
are serviced. Any interrupt that occurs during this time is latched as pending and is not serviced until after
the final delay-slot instruction. See Section 9.3.4, “Non-Interruptible Instruction Sequences,” on page 9-10
for more information.
4.4
This section presents the entire DSP56800E instruction set in tabular form. The tables show the instruction
mnemonics, supported operands, and addressing modes for each instruction. The number of instruction
cycles that each operation takes to execute and the number of program words that it occupies is also listed.
With these tables, it is easy to determine the appropriate instruction for a given application.
4.4.1
The entries in the instruction summary tables give the name of the operation (the instruction mnemonic),
the legal operands, cycle and word counts, and a brief description of the operation. The general form
appears in Table 4-14.
The operands are specified using the register and immediate values that are allowed, or, when there are a
number of options, using shorthand notation. This notation, which is used to describe a set of registers, is
explained in Section 4.4.2, “Register Field Notation.”
The summary tables and the notation definitions make it possible to determine whether or not a particular
instruction is legal. For the MAC instruction in Table 4-14, for example, we can determine that the
following are valid DSP56800E instructions:
The (+) in the operand entry for MAC indicates that an optional “+” or “–” sign can be specified before the
input register combination. If a “–” is specified, the multiplication result is negated.
Freescale Semiconductor
MAC
•
•
•
Operation
BFCHG, BFCLR, or BFSET instructions (including the ANDC, EORC, NOTC, and ORC
instruction aliases) that operate on the R0, R1, or N registers
CLR.W or TST.W on either the R0, R1, or N registers
Any two instructions in the delay slots (including any hardware interlocks) with a total execution
time greater than 3 cycles
Instruction Set Summary
Delayed Instructions and Interrupts
Using the Instruction Summary Tables
MAC
MAC
MAC
(±)FFF1,FFF1,FFF
X0,Y0,A
+X0,Y0,A
-X0,Y0,A
Table 4-14. Sample Instruction Summary Table
Operands
Instruction Set Introduction
; A + X0*Y0 -> A
; A + X0*Y0 -> A
; A - (X0*Y0) -> A
1
C
1
W
Fractional multiply-accumulate; multiplication result
optionally negated before accumulation
Comments
Instruction Set Summary
4-15