dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 698

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Bcc instruction 4-9, 4-14, 4-45, 9-10, A-57 to A-58
BFCHG instruction 4-8, 4-11, 4-14 to 4-15, 4-42, 7-1,
BFCLR instruction 4-8, 4-11, 4-14 to 4-15, 4-43, 7-1,
BFSET instruction 4-8, 4-11, 4-14 to 4-15, 4-43, 7-1,
BFTSTH instruction 4-8, 4-43, 7-1, A-68
BFTSTL instruction 4-8, 4-44, 7-1, A-71
bit-manipulation instructions 4-8, 4-42, 7-1, 8-9
BR1CLR operation 7-8 to 7-10
BR1SET operation 7-8 to 7-10
BRA instruction 4-9, 4-14, 4-45, A-74
BRAD instruction 4-9, 4-13 to 4-14, 4-45, A-75
BRCLR instruction 4-9, 4-44, 7-1, 7-9, 9-10, A-77
breakpoints and breakpoint counter 11-8, 11-11
BRSET instruction 4-9, 4-44, 7-1, 7-9, 9-10, A-80
BSR instruction 4-9, 4-14, 4-45, 8-11, 8-15, A-83
bus and bit-manipulation unit 7-1
byte addresses 3-16, 6-7
byte ordering 6-8
byte pointers 3-18, 3-21 to 3-22, 6-4, 6-11, 6-13
byte variable alignment 3-16
C
C programming language 1-1 to 1-2, 6-11
C, see accumulator registers (A, B, C, and D) and carry
C0, see least significant product registers (A0, B0, C0,
C1, see most significant product registers (A1, B1, C1,
C2, see extension registers (A2, B2, C2, and D2)
carry bit (C) 8-9
CCPL, see current core interrupt priority level (CCPL)
CCR, see condition code register (CCR)
CDBR, see core data bus for reads (CDBR)
CDBW, see core data bus for writes (CDBW)
change-of-flow instructions 4-45
change-of-flow trace buffer 11-8, 11-11
circular buffer 6-20 to 6-22
CLB instruction 4-6, 4-40, 5-37, A-84
CLR instruction 4-3, 4-31, 4-48 to 4-49, A-86
CLR.B instruction 4-3, 4-31, A-89
CLR.BP instruction 4-3, 4-31, A-90
CLR.L instruction 4-3, 4-32, A-92
CLR.W instruction 4-3, 4-15, 4-32, A-94
CM, see condition code mode bit (CM)
CMP instruction 4-3, 4-33, 4-48, A-96
CMP.B instruction 4-3, 4-33, A-99
CMP.BP instruction 4-3, 4-33, A-101
CMP.L instruction 4-3, 4-33, A-103
CMP.W instruction 4-3, 4-34, A-105
CMPA instruction 4-6 to 4-7, 4-41, A-109
Index-ii
A-59
A-62
A-65
bit (C)
and D0)
and D1)
DSP56800E Core Reference Manual
CMPA.W instruction 4-6 to 4-7, 4-41, A-110
comparison operations 5-16
condition code mode bit (CM) 8-7, B-3
condition code register (CCR) 8-7, B-4
condition codes
conditional transfer instructions 4-27
convergent rounding 5-43 to 5-44, 8-6
core data bus for reads (CDBR) 2-7
core data bus for writes (CDBW) 2-7
core programming model 2-2, 3-1
current core interrupt priority level (CCPL) 9-3, 10-24
D
D, see accumulator registers (A, B, C, and D)
D0, see least significant product registers (A0, B0, C0,
D1, see most significant product registers (A1, B1, C1,
D2, see extension registers (A2, B2, C2, and D2)
data alignment 3-13
data arithmetic logic unit (data ALU) 5-1
data formats 3-6
data limiter 2-8, 5-2, 5-39, 8-10
data register data alignment 3-14
data registers (X0, Y1, and Y0) 2-8, 5-2 to 5-3
data size suffixes 3-9
data structures 6-11
data types 5-15
data-memory execution mode 8-6
debug processing state 9-1, 9-13, 11-6
DEBUGEV instruction 4-10, 4-14, 4-47, A-111
debugging 1-2, 2-1, 11-1
DEBUGHLT instruction 4-10, 4-14, 4-47, A-112
DEC.BP instruction 4-3, 4-34, A-113
DEC.L instruction 4-3, 4-34, A-115
calculation 5-38
modes 5-38
in accumulators 3-13
in AGU registers 3-14
byte variables 3-16
in data registers 3-14
long-word variables 3-17, 3-19, 9-9
in memory 3-15
word variables 3-17
accumulator registers, see accumulator registers (A,
input registers, see data registers (X0, Y1, and Y0)
overview of registers 3-3
signed fractional 3-6
signed integer 3-6
unsigned fractional 3-7
unsigned integer 3-6
32-bit 5-38, 8-7
36-bit 5-38, 8-7
and D0)
and D1)
B, C, and D)
Freescale Semiconductor