dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 281

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10
Instruction Pipeline
The DSP56800E architecture is built around an eight-stage execution pipeline. The eight stages overlap
instruction fetches, operand fetches, and instruction execution, resulting in higher execution throughput.
The eight stages of the pipeline are shown in Figure 10-1.
Instructions typically require 7 or 8 clock cycles to be fetched, to be decoded, and to finish execution,
depending on their complexity. Most instructions will complete and be retired (their results written back
and condition codes updated) by the end of the Execute stage of the pipeline. Some more complex
instructions require additional processing and are retired in the Execute 2 stage. AGU arithmetic
instructions complete execution in the Address Generation stage. Although it takes as many as 8 clock
cycles to fill the pipeline and to complete the execution of the first instruction, subsequent instructions
typically complete execution on each clock cycle thereafter.
Although the execution pipeline is composed of many stages, its operation is largely hidden from the user.
Knowledge of the pipeline is useful, however, because certain code sequences can introduce pipeline
dependencies. These dependencies, and the resultant pipeline stalls, can affect overall performance if they
are not addressed. The following sections describe the pipeline in detail, including those circumstances that
can result in pipeline dependencies.
Freescale Semiconductor
Figure 10-1. DSP56800E Eight-Stage Pipeline
Execute and Operand Fetch (EX)
Operand Pre-Fetch 2 (OP2)
Instruction Pipeline
Address Generation (AG)
Instruction Decode (ID)
Instruction Fetch (IF)
Pre-Fetch 1 (P1)
Pre-Fetch 2 (P2)
Execute 2 (EX2)
10-1