dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 243

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

OMR
Freescale Semiconductor
RESET
TYPE
NL
Bit 15
Reserved
Bits 14–9
CM
Bit 8
XP
Bit 7
SD
Bit 6
R
Bit 5
SA
Bit 4
EX
Bit 3
Reserved
Bit 2
MB and MA
Bits 1–0
Name
BIT 15
NL
rw
0
14
0
When a bit of the OMR is changed by an instruction, a delay of
2 instruction cycles is necessary before the new mode comes into effect.
When individual bits in the OMR are modified, the BFCLR, BFCHG, or
BFSET instructions should be used instead of a MOVE instruction to
prevent the accidental modification of other bits.
Nested Looping—Indicates whether a nested
hardware DO loop is active or whether HWS has
been written to at least two times without being
read
Reserved
Condition Code Mode—Selects whether 36-bit
or 32-bit values are used for condition codes
X or P Memory Select—Determines the mem-
ory space from which instructions are fetched
Stop Delay—Selects length of wake-up time
from stop mode
Rounding—Selects the rounding method
Saturation—Enables automatic saturation in
the data ALU
External X Memory Select—Forces all data
memory access to be in external memory
Reserved
Operating Mode—Selects the memory map
and operating mode
13
0
12
0
Description
11
0
Table 8-1. OMR Bit Descriptions
Operating Mode Register
10
0
Program Controller
9
0
NOTE:
CM
rw
8
0
XP
rw
7
0
Program Controller Programming Model
0 = Convergent rounding.
0 = No nested DO loop active.
1 = Nested DO loop active.
Note: See Section 8.4, “Hardware Stack.”
These bits are reserved and always read
zero.
0 = 36-bit values are used.
1 = 32-bit values are used.
0 = Fetched from P (program) memory.
1 = Fetched from X (data) memory.
Dependent on individual chip’s implementa-
tion.
1 = Two’s-complement rounding.
0 = Saturation disabled.
1 = Saturation enabled.
0 = Internal data memory accesses.
1 = Data memory accesses are external.
This bit is dependent on the individual chip's
implementation.
This bit is reserved and always reads zero.
This bit is dependent on the individual chip’s
implementation.
SD
rw
6
0
rw
R
5
0
SA
rw
4
0
Settings
EX
rw
—
3
2
0
MB
rw
—
1
BIT 0
MA
rw
—
8-5