dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 318

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

JTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
An unlocking sequence must first be executed by the core to gain access to the Enhanced OnCE module.
This prevents accidental access to the Enhanced OnCE resources. Core access to the Enhanced OnCE
module can optionally be disabled via the JTAG port to prevent programs from affecting the Enhanced
OnCE module’s operation.
11.3.3
The DSP56800E supports two instructions, DEBUGEV and DEBUGHLT, that will trigger actions in the
Enhanced OnCE module when executed by the DSP56800E core. The DEBUGEV instruction causes a
debugging event to be generated, similar to the generation of a breakpoint trigger. The DEBUGHLT
instruction is used to halt the core, placing it in the Debug processing state, where state information can be
easily read and modified.
11.4
The DSP56800E core supports six different processing states (see Table 11-1).
11.4.1
The Debug processing state is a state where the core is halted, breakpoints and other resources can be
initialized and setup for debugging, and on-chip registers and memory locations can be examined and
modified. The chip is often placed in the Debug processing state to initialize the Enhanced OnCE module
for a debug system. It is also possible for the core to enter the Debug processing state immediately upon
exiting reset to setup a debug session before the core begins executing instructions.
Any of the following can place the core in the Debug processing state:
11-6
•
•
•
Normal
Reset
Exception
Wait
Stop
Debug
Hardware reset with JTAG DEBUG_REQUEST in the JTAG Instruction Register (IR)
JTAG DEBUG_REQUEST placed in the JTAG IR during
— STOP mode
— WAIT mode
— wait states
Pulling the core debug_req_b pin low for three peripheral clock cycles
State
Enhanced OnCE and the Processing States
Other Supported Interactions
Using the Debug Processing State
The state of the core where instructions are normally executed.
The state of interrupt processing, where the core transfers program control from its cur-
A low power state where the core, the interrupt machine, and most (if not all) of the
The state where the core is forced into a known reset state. The first program instruction
is fetched upon exiting this state.
rent location to an interrupt service routine using the interrupt vector table.
A low power state where the core is shut down but the peripherals and the interrupt
machine remain active.
peripherals are shut down.
The state where the core is halted and all registers in the Enhanced On-Chip Emulation
(EOnCE) port of the processor are accessible for program debug.
DSP56800E Core Reference Manual
Table 11-1. Processing States
Description
Freescale Semiconductor