dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 32

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Introduction
The DSP56800E’s efficient instruction set and bus structure, extensive parallelism, on-chip program and
data memories, and advanced debugging and test features make the core an excellent solution for real-time,
embedded DSC and control tasks. It is the perfect choice for wireless and wireline DSC applications,
digital and industrial control, or any other embedded-controller application that needs high-performance
processing.
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The DSP56800E core consists of a data arithmetic logic unit (ALU), an address generation unit (AGU), a
program controller, a bit-manipulation unit, an Enhanced On-Chip Emulation module (Enhanced OnCE),
and associated buses. Figure 1-1 on page 1-3 shows a diagram of the DSP56800E core.
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High Code Density—The base instruction word size for the DSP56800E is only 16 bits, with
multi-word instructions for more complex operations, resulting in optimal code density. The
instruction set emphasizes efficient control programming, which accounts for the largest portion of
an application.
Multi-Tasking Support—Implementing a real-time operating system or simple multi-tasking is
much easier on the DSP56800E than on most DSCs. The architecture provides full support for a
software stack, fast 32-bit context saves and restores to and from the system stack, atomic
test-and-set operations, and four prioritized software interrupts.
Precision—The DSP56800E core enables precise DSC calculations. Enough precision for 96 dB
of dynamic range is provided by 16-bit data paths. Intermediate values in the 36-bit accumulators
can range over 216 dB.
Hardware Looping—Two types of zero-overhead hardware looping are provided, enhancing
performance and making loop-unrolling techniques unnecessary.
Parallelism—Each on-chip execution unit, memory device, and peripheral operates independently
and in parallel. Because of the high level of parallelism, the following can be executed in a single
instruction:
— Fetching the next instruction
— A 16-bit × 16-bit multiplication with 36-bit accumulation
— Optional negation, rounding, and saturation of the result
— Two 16-bit data moves
— No-overhead hardware looping
— Two address pointer updates
Invisible Instruction Pipeline—The eight-stage instruction pipeline provides enhanced
performance while remaining essentially invisible to the programmer. Developers can program in
high-level languages such as C without being concerned about the pipeline, even as they benefit
from the pipeline’s throughput of one instruction per cycle.
Low Power Consumption—Implemented in CMOS, the DSP56800E inherently consumes very
little power. In addition, the core architecture supports two low-power modes, STOP and WAIT,
which can provide even more power savings. The power management implementation can shut off
unused sections of logic.
Real-Time Debugging—Freescale’s Enhanced On-Chip Emulation technology (Enhanced
OnCE™) allows simple, inexpensive, non-intrusive, and speed-independent access to the internal
state of the DSP56800E core. By using Enhanced OnCE, programmers have full control over the
processor’s operation, simplifying and speeding debugging tasks without having to halt the core.
Architectural Overview
DSP56800E Core Reference Manual
Freescale Semiconductor