dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 323

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

11.4.3.2.3
The breakpoint unit combining logic supports combinations of breakpoints. This allows for the execution
of OR and AND operations as well as the sequencing of more than one breakpoint.
11.4.3.3
This submodule also provides the capability for full-speed instruction stepping. A 24-bit instruction step
counter provides for up to 16,777,216 instructions to be executed at full speed before the processor core is
interrupted (or halted) and enters the Debug processing state. This capability allows the user to single step
through a program or to execute whole functions at a time.
This counter can be used very effectively in combination with the Breakpoint Unit capabilities for more
complex debugging scenarios. This will be demonstrated in detail in Section 11.4.4, “Effectively Using the
Debug Port,” on page 11-13.
11.4.3.4
To ease debugging activity and to help keep track of program flow, a read-only buffer is provided that
tracks the change-of-program-flow execution history of an application. It can store the address of the most
recent change-of-flow instruction as well as the addresses of the previous seven change-of-flow
instructions. The trace buffer is intended to provide a snapshot of the recent execution history of the
DSP56800E processor core. This buffer is capable of capturing any combination of the following
execution flow events:
Sequential program flow can be assumed to have occurred between the recorded instructions, so it is
possible for the user to reconstruct the program execution flow extending back quite a number of
instructions. To complete the execution history, a circular pointer is used to indicate the location of the
buffer that holds the address of the most recent change-of-flow instruction. The pointer is then
decremented while reading the eight buffer locations to obtain a sequential trace of these instructions back
in time.
The Enhanced OnCE module provides flexible control over the trace buffer. Starting and stopping capture
into the buffer is programmable, so capture only occurs when it is needed. Once the eight-position buffer is
filled, there are several programmable options for what action the Enhanced OnCE module takes:
11.4.3.5
The Realtime Data Transfer Unit enables the user to transmit data from the DSP56800E processor core to
the external host through the JTAG port, and enables the core to receive data from the external host, in
real-time program execution.
Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
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Interrupts—captures the address of the interrupt vector and the target address of returns
Subroutines—captures the target address of JSR and BSR instructions
Conditional branches, whether taken or not, forward or backward—captures the target addresses for
the Bcc, Jcc, BRSET, and BRCLR instructions
No action—Buffer continues to capture change of flows.
Halt buffer—Buffer capture is stopped.
Enter debug—Buffer capture is stopped and core enters debug mode.
Interrupt—Buffer capture is stopped and an interrupt occurs.
Step Counter
Change-of-Flow Trace Buffer
Realtime Data Transfer Unit
Combining Logic
Enhanced OnCE and the Processing States
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