dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 482
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dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 482 of 706
- Download datasheet (4Mb)
EORC
Operation:
#xxxx ⊕ X:<ea> → X:<ea>(no parallel move)
#xxxx ⊕ D → D(no parallel move)
where ⊕ denotes the logical exclusive OR operator
Implementation Note:
Description: Perform a logical exclusive OR operation on a 16-bit immediate data value with the destination oper-
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Instruction Fields:
A-138
This instruction is implemented by the assembler as an alias to the BFCHG instruction, and it uses the
16-bit immediate value as the bit mask. This instruction will dis-assemble as a BFCHG instruction.
and (D), and store the results back into the destination. C is also modified as described in “Condition
Codes Affected.” This instruction performs a read-modify-write operation on the destination and re-
quires two destination accesses.
EORC
Prior to execution, the 16-bit X memory location X:$5000 contains the value $5555. Execution of the
instruction tests the state of bits 4–11 in X:$5000, does not set C (because all of the selected bits were
not set), and then complements the bits.
For destination operand SR:
For other destination operands:
L
C
If all bits in the mask are cleared, the instruction executes two NOPs and sets the C bit.
Refer to the section on the BFCHG instruction for legal operand and timing information.
Before Execution
X:$5000
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
SR
P4
14
All SR bits except bits 14–10 are updated with values from the bitfield unit.
Bits 14–10 of the mask operand must be cleared.
Cleared if at least 1 bit specified by the mask is not set
#$0FF0,X:$5000; Exclusive OR with immediate data
13
P3
Logical Exclusive OR Immediate
P2
12
5555
0300
MR
DSP56800E Core Reference Manual
P1
11
P0
10
I1
9
Assembler Syntax:
EORC
EORC
I0
8
SZ
7
6
L
5
E
After Execution
X:$5000
#iiii,X:<ea>
#iiii,D
U
4
CCR
SR
N
3
2
Z
5AA5
0300
Freescale Semiconductor
V
1
(no parallel move)
(no parallel move)
C
0
EORC
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