dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 305

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

This case is demonstrated in Figure 10-13. The following notation is used in the figure:
The single-cycle instruction n1 in this example writes to the status register, lowering the CCPL. The actual
write to the CCPL occurs at the end of cycle #7 (the Execute 2 stage is not used by instruction n1). In cycle
#8, the program interrupt controller arbitrates the already pending interrupts, but now with a lower CCPL.
An interrupt is now recognized as valid, and interrupt processing begins.
The exact calculation of the time to recognize and process a pending interrupt after modifying the CCPL is
measured from the decode of instruction n1, which modifies CCPL (the beginning of cycle #4 in
Figure 10-13), to the first decode cycle of the first instruction that is fetched from the vector table after a
pending interrupt is recognized (beginning of cycle #13):
In the preceding equation, the “Instruction at Int Req” is defined as the instruction in the Instruction
Decode stage of the pipeline when the pending interrupt is at the Int Req stage of the pipeline. In this
example, the instruction is n6. The “remaining execution time of ‘Instruction at Int Req’” is the number of
cycles from the time that the interrupt request reaches the Int Req stage for the pipeline to the time when
this instruction completes the pipeline’s decode stage.
Freescale Semiconductor
EE
•
•
•
Pipeline
Int Arbitr
Int Req
Stage
OP2
EX2
n1 is a 1-cycle instruction that modifies the SR register.
p0 and p1 are the 2 instruction cycles that are executed immediately before instruction n1. They can
be a single multi-cycle instruction or two single-cycle instructions.
ii0 is the first word that is fetched from the interrupt vector table for the interrupt that is serviced.
In Figure 10-13, ii0 is the first word of the JSR instruction.
Delay =
AG
EX
P1
P2
ID
IF
n1 n2 n3 n4 n5 n6 n7
p0 n1 n2 n3 n4 n5 n6
p1 p0 n1 n2 n3 n4 n5
1
p1 p0 n1 n2 n3 n4
2
Execution time of instruction n1
+ 3 clock cycles for n1 to reach the end of the Execute phase
+ 1 clock cycle for arbitration with updated CCPL
+ remaining execution time of “Instruction at Int Req” (see following discussion)
+ 3 clock cycles for NOPs forced into pipeline
+ any pipeline core stalls due to data memory dependencies or wait states for p0 and p1
+ wait states due to program fetches of n2 through n5
– 1 clock cycle if n1 is a 2-cycle instruction that writes an immediate to the SR
p1 p0 n1 n2 n3
3
p1 p0 n1 n2
4
Figure 10-13. Delay When Updating the CCPL
p1 p0 n1
5
CCPL, Enabling Interrupts
Write to SR Changes the
p1 p0
6
7
n8
n7
n6
n5
n4
n3
n2
—
8
i
Instruction Pipeline
n9
n8
n7
n6
n5
n4
n3
n2
9
i
10 11 12 13 14 15 16 17 18 19 20 21
n9
n8
n6
n5
n3
ii0
—
n4
Instruction Cycle
n9
n6
n5
n4
ii1
ii0
—
—
n6
n5
ii1
ii1
ii0
—
—
—
ii1
ii1
ii1
jsr
—
—
—
n6
Pipeline During Interrupt Processing
Arbitrates with NEW CCPL, and
ii2
ii1
ii1
jsr
jsr
—
—
—
Pending Interrupt Is Serviced
jsr
jsr
jsr
ii3
ii2
ii1
—
—
jsr
jsr
jsr
jsr
ii4
ii3
ii2
—
ii4
ii3
ii2
jsr
jsr
jsr
—
•
ii4
ii3
ii2
jsr
jsr
—
•
•
ii4
ii3
ii2
jsr
—
•
•
•
ii3
ii4
ii2
—
•
•
•
•
ii4
ii3
ii2
•
•
•
•
•
10-25