dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 307

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Operand dependencies occur in the example between n5 and n6 and between n7 and n8. Instruction n9
removes a potential dependency by resetting the pipeline to the Normal state. Note that no operand
dependency exists with the D register between n4 and n5 because it is used only in accumulation, not
multiplication. Note also that n7 completes in Execute 2, since the pipeline is forced Late by n6.
It should be noted that there are no pipeline effects when the data ALU executes instructions using Late
Execution as long as the following instruction neither writes the results to memory nor depends on the
condition codes that are generated.
This situation is demonstrated in Example 10-4. As the associated pipeline in Table 10-5 on page 10-28
shows, there are no pipeline dependencies. Note that n2 and n3 in this example complete in the Execute 2
stage because the pipeline is placed in the Late state by n1.
Freescale Semiconductor
Pipeline
Int Arbitr
Int Req
Stage
OP2
EX2
AG
EX
P1
P2
ID
IF
NOP
ADD
SUB
MPY
MAC
MPY
AND.W
ASLL.W
ASLA
MPY
MAC
SUB
ASL
TFRA
MOVE.W
ADD
n1 n2 n3
1
n1 n2
2
Example 10-4. Case with No Data ALU Pipeline Dependencies
n1
3
X0,A
A,B
B1,C1,D
X0,Y0,D
D1,X0,C
Y0,C
#3,C
R0
C1,D1,C
Table 10-4. Data ALU Operand Dependency Pipeline
X0,Y0,A
Y1,A
A
R2,R1
A,X:(R0)+
X0,A
nop add sub mpy mac
n4
n3
n2
4
Example 10-3. Data ALU Operand Dependencies
n5
n4
n3
—
5
add sub mpy mac
n6
n5
n4
—
6
add sub mpy mac
n7
n6
n5
—
7
; n1: Non-data ALU (restores to Normal state)
; n2: Normal Execution (Execute phase)
; n3: Normal Execution (Execute phase)
; n4: Two-Stage (Execute and Execute 2)
; n5: Two-Stage (Execute and Execute 2)
; n6: Two-Stage (Execute and Execute 2)
; n7: Late Execution (Execute 2 phase)
; n8: Two-Stage (Execute and Execute 2)
; n9: Non-data ALU (restores to Normal state)
; n10: Two-Stage (Execute and Execute 2)
; n1: performed in Execute and Execute 2
; n2: Late Execution (Execute 2 phase)
; n3: Late Execution (Execute 2 phase)
; n4: Non-data ALU (restores to Normal state)
; n5: (no dependency)
; n6: Normal Execution (Execute phase)
Instruction Pipeline
add sub mpy mac
n8
n7
n6
—
8
n9
n8
n7
—
—
9
Instruction Cycle
mpy and
10
—
—
—
—
—
mpy and
mpy mac
n10
11
n9
n8
—
mpy and
n10
12
n9
—
—
•
Pipeline Dependencies and Interlocks
mpy
asll asla mpy
13
—
—
—
—
—
mpy and
n10
asll asla mpy
14
—
—
•
•
asll
15
—
•
•
•
asll
16
—
—
•
•
•
•
mpy
asll
17
—
•
•
•
•
•
mpy
18
—
•
•
•
•
•
•
mpy
19
•
•
•
•
•
•
•
20
•
•
•
•
•
•
•
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10-27
21
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