dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 347

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Table A-3 shows the register set that is available for use in data ALU arithmetic operations. The most
common field that is used in this table is FFF.
Freescale Semiconductor
Register Field
Register
(or SSS)
FFF1
Field
EEE
FFF
DD
FF
F1
FIRA
RRR
fff
M01
F
Rn
N3
Rj
Registers in this
A1, B1, C1, D1
Registers in this
X0, Y0, Y1
X0, Y0, Y1
X0, Y0, Y1
X0, Y0, Y1
A, B, C, D
A, B, C, D
A, B, C, D
A, B, C, D
R0, R1, R2, R3
A1, B1
Field
A, B
Table A-2. Address Generation Unit (AGU) Registers
Y
Y
R0–R5
R0–R5
Field
FIRA
M01
SP
N3
N
N
Table A-3. Data ALU Registers
Eight data ALU registers—four 36-bit accumulators, one 32-bit long regis-
ter Y, and three 16-bit data registers that are accessible during data ALU
operations.
Seven data ALU registers—four 16-bit MSP portions of the accumulators
and three 16-bit data registers that are accessible during data ALU opera-
tions.
This field is identical to the HHH (source) field. It is very similar to FFF, but
it indicates that the MSP portion of the accumulator is in use. Note the
usage of A1, B1, C1, and D1.
Seven data ALU registers—four accumulators and three 16-bit data regis-
ters that are accessible during data ALU operations.
This field is similar to FFF but is missing the 32-bit Y register. Used for
instructions where Y is not a useful operand (use Y1 instead).
Four 36-bit accumulators and one 32-bit long register that are accessible
during data ALU operations.
Four 36-bit accumulators that are accessible during data ALU operations.
Three 16-bit data registers.
Two 36-bit accumulators that are accessible during parallel move instruc-
tions and some data ALU operations.
The 16-bit MSP portions of two accumulators that are accessible as source
operands in parallel move instructions.
Instruction Set Details
Eight AGU registers that are available as pointers for addressing and
address calculations
Seven AGU registers that are available as sources and destinations
for move instructions
Four pointer registers that are available as pointers for addressing
One index register that is available only for the second access in dual
parallel read instructions
Address modifier register
Fast interrupt return register
Comments
Comments
A-3