dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 373

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

AND.L
Operation:
S • D → D
where • denotes the logical AND operator
Description: Perform a logical AND operation on the source operand and the destination operand, and store the re-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
6
sult in the destination. This instruction is a 32-bit operation. If the destination is a 36-bit accumulator,
the AND operation is performed on the source and bits 31–0 of the accumulator. The remaining bits
of the destination accumulator are not affected. If the source is a 16-bit register, it is first internally
concatenated with 16 zero bits to form a 32-bit operand. If the source is an immediate 5-bit constant,
it is first zero extended to form a 32-bit operand. When the destination is an accumulator, bits 35–32
remain unchanged. The result is not affected by the state of the saturation bit (SA).
This instruction is used for the logical AND of two registers or of a register and a small immediate
value. The ANDC instruction is appropriate for performing an AND operation on a 16-bit immediate
value and a register or memory location.
AND.L
Prior to execution, the 32-bit Y register contains the value $7F00:00FF, and the 36-bit A accumulator
contains the value $6:1234:5678. The AND.L Y,A instruction performs a logical AND operation on
the 32-bit value in the Y register and on bits 31–0 of the A accumulator (A10), and it stores the 36-bit
result in the A accumulator. Bits 35–32 in the A2 register are not affected by this instruction.
N
Z
V
LF
15
— Set if bit 31 of accumulator or register result is set
— Set if bits 31–0 of accumulator or register result are zero
— Always cleared
(no parallel move)
1234
7F00
P4
14
A1
Y1
Y,A
13
P3
SR
P2
12
MR
P1
11
00FF
5678
0302
A0
Y0
P0
10
Instruction Set Details
; logically AND Y with A10
I1
AND Long
9
Assembler Syntax:
AND.L
I0
8
SZ
7
After Execution
6
L
A2
6
5
E
S,D
U
4
CCR
7F00
1200
A1
Y1
N
3
(no parallel move)
SR
2
Z
V
1
00FF
0300
0078
C
0
A0
Y0
AND.L
A-29