dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 340

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

JTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
11.5.2.1
As described in the IEEE 1149.1a-1993 specification, a JTAG TAP requires a minimum of 4 pins to
support TDI, TDO, TCK, and TMS signals. TDI and TDO are the serial input and output, respectively.
TCK is the serial clock input and TMS is an input used to selectively step through the JTAG state machine.
A fifth pin TRST is an optional asynchronous reset pin for the chip JTAG TLM system (refer to the
particular chip users manual to see if this pin is available).
These pins for the core JTAG port are CORE_TDI, CORE_TDO, TCK, TMS. The core pin functions are
described in Table 11-15. The core JTAG TAP also uses the TLM_RESET_B pin to provide an
asynchronous reset of the core JTAG port from the chip JTAG TLM. If TRST is present on a chip the core
TLM_RESET_B pin will always be asserted whenever TRST is asserted.
The core JTAG TAP must be enabled (CORE_TAP_EN asserted) before the core JTAG state machine will
follow the transitions and state of the TMS pin. The core TAP will only leave the Run-Test/Idle state to
enter the DR or IR states while the CORE_TAP_EN pin is asserted, and will return to Run-Test/Idle when
the pin is deasserted in the Update-DR state.
11-28
CORE_TDI
CORE_TDO
TCK
TMS
TLM_RESET_B
CORE_TAP_EN
CORE_TLM_SEL
Pin Name
JTAG Terminal Description
Test Data Input—This input pin to the core provides a serial input data
stream to the core TAP and the EOnCE module. It is sampled on the rising
edge of TCK.
Test Data Output—This output pin provides a serial output data stream
from the core TAP and the EOnCE module. It is driven in the Shift-IR and
Shift-DR controller states of the core TAP state machine.
Test Clock Input—This input pin provides the clock to synchronize the test
logic and shift serial data to and from the core EOnCE/JTAG port. When
accessing the EOnCE module through the JTAG TAP, the maximum
frequency for TCK is 1/4 the maximum frequency specified for the Hawk
Version 2 core.
Test Mode Select Input—This input pin is used to sequence the core JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK.
Test Reset—This input pin, comes from the chip TLM and provides an
asynchronous reset signal to the JTAG TAP controller,.
Core TAP Enable—This input, comes from the chip TLM module and gates
the input TMS signal to force the TAP controller to the Run-Test/Idle state
when the enable signal is deasserted (logic 0). When the enable signal is
asserted, the TAP controller will follow the transitions and state of the input
pin TMS signal.
Core TLM Selects—This output from the core JTAG TAP selects the chip
TLM register for the data register to be scanned.
Table 11-15. JTAG Pin Descriptions
DSP56800E Core Reference Manual
Pin Description
Freescale Semiconductor