dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 268

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Processing States
On devices with a computer operating properly (COP) timer, it is also possible for the COP timer to assert
the RESET signal if the timer reaches zero, forcing the core into the reset processing state.
The DSP56800E core remains in the reset processing state until the cause for reset is de-asserted. When the
reset trigger is deasserted, the following occurs:
The DSP56800E core enters the normal processing state upon exiting reset. It is also possible for the core
to enter the debug processing state upon exiting reset when system debug is underway. See Section 9.6,
“Debug Processing State.”
9.3
In the exception processing state, the DSP56800E core recognizes and processes interrupts and exceptions.
Interrupts and exceptions can be generated by conditions inside the core, such as illegal instructions, or
from external sources, such as an interrupt request signal. When an exception occurs, control is transferred
from the currently executing program to an interrupt service routine. Upon entering the interrupt service
routine, the core exits the exception processing state and enters the normal processing state. When the
interrupt routine is terminated, the interrupted program resumes execution.
In digital signal processing, some common uses of interrupts are to transfer data between the data memory
and a peripheral device or to begin execution of a DSC algorithm upon the reception of a new sample.
Interrupts are also useful for system calls in an operating system and for servicing peripherals. An interrupt
that is enabled can also be used to exit the DSC’s low-power wait processing state.
There are many sources for interrupts on the DSP56800E Family of chips, and some of these sources can
generate more than one interrupt. Interrupt requests can be generated from conditions within the core, from
the on-chip peripherals, or from external pins. The DSP56800E core features a prioritized interrupt vector
scheme to provide faster interrupt servicing. The interrupt priority structure is discussed in Section 9.3.1,
“Interrupt Priority Structure.”
Several types of exceptions are supported: interrupts, which are generated by the core, the debug port,
on-chip peripherals or interrupt request pins, and instruction level exceptions, which are caused by the
execution of an instruction. The DSP56800E supports an unlimited number of exceptions. Core interrupts
and instruction level exceptions have a fixed priority level (there are software interrupt instructions for
requesting an interrupt at each of the five priority levels); peripheral and debug port interrupts may be
programmed to one of three priority levels or be disabled.
The following sections discuss the interrupt priority levels, the ways in which interrupts are processed, and
the various sources for interrupts and exceptions.
9-2
1. The internal registers are set to their reset state:
2. The chip operating mode bits (MA and MB) in the OMR are loaded from external mode
3. The core begins instruction execution at the program memory address that is defined by the
— The modifier register (M01) is set to $FFFF.
— The status register’s (SR) loop flag and condition code bits are cleared.
— The interrupt mask bits (I1 and I0) in the status register are both set to one.
— All bits in the operating mode register (except MA and MB) are cleared.
select pins, establishing the operating mode of the chip.
address of the reset vector that is provided to the core. There may be different vector
addresses for different reset sources, such as the RESET signal or the COP and RTI timer.
The reset vector or vectors are specific to a particular DSP56800E–based device. Consult
the appropriate device’s user’s manual for details.
Exception Processing State
DSP56800E Core Reference Manual
Freescale Semiconductor