dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 269

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

9.3.1
The DSP56800E architecture supports five interrupt priority levels. Levels LP, 0, 1, and 2, in ascending
priority, are maskable. Level 3 is the highest priority and is non-maskable. Priority levels 0–2 are used for
programmable interrupt sources, such as peripherals and external interrupt requests. The lowest priority
level, LP, can only be generated by the SWILP instruction. Level 3 interrupts are generated by the core.
Table 9-1 shows the different interrupt priority levels.
When exceptions or interrupts occur simultaneously, higher-priority exceptions take precedence. It is also
possible for a higher-priority exception to interrupt the interrupt handler of a lower-priority exception.
Reset conditions take precedence over all interrupt priorities. If a reset occurs, the chip immediately enters
the reset processing state.
The current core interrupt priority level (CCPL) defines which interrupt priority levels will be accepted and
which will be rejected by the core. Interrupt sources with a priority level that is equal to or greater than the
CCPL are accepted. Interrupt sources with a priority level that is lower than the CCPL are rejected.
Non-maskable interrupts (level 3) are always accepted. The CCPL is determined from the I1 and I0 bits in
the status register. Table 9-2 shows the CCPL values.
Freescale Semiconductor
I1
0
0
1
1
IPL
LP
0
1
2
3
I0
0
1
0
1
Interrupt Priority Structure
Non-maskable
Description
Maskable
Maskable
Maskable
Maskable
CCPL
0
1
2
3
IPL 0, 1, 2, 3
Exceptions
and SWILP
IPL 1, 2, 3
Accepted
Table 9-2. Current Core Interrupt Priority Levels
IPL 2, 3
IPL 3
Table 9-1. Interrupt Priority Level Summary
Priority
Highest
Lowest
.
.
.
Exceptions
Processing States
and SWILP
and SWILP
IPL 0, 1, 2
IPL 0 and
Masked
IPL 0, 1
SWILP
SWILP instruction
On-chip peripherals, IRQA and IRQB,
On-chip peripherals, IRQA and IRQB,
Enhanced OnCE interrupts
On-chip peripherals, IRQA and IRQB,
Enhanced OnCE interrupts
Illegal instruction, hardware stack overflow, SWI instruction,
Enhanced OnCE interrupts, misaligned data access
None
The interrupt controller accepts any unmasked
interrupt, including the SWILP.
The interrupt controller accepts all non-maskable
interrupts and any unmasked interrupts that are
programmed at level 1 or 2.
The interrupt controller accepts all non-maskable
interrupts and any unmasked interrupts that are
programmed at level 2.
The interrupt controller only accepts non-maskable
interrupts (level 3).
Interrupt Sources
Exception Processing State
Comments
SWI #0
SWI #1
SWI #2
instruction
instruction,
instruction,
9-3