dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 328

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

JTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
11.4.4.2.1
The full set of breakpoint triggers which can be created by this unit is shown in Table 11-4 and Table 11-5,
where Table 11-4 contains most of the unit’s triggering capability and is combined with the capabilities of
Table 11-5 to get the final Breakpoint Unit Trigger generated from the unit.
The notation for these tables is explained below:
11-16
CDB — Data Value
expr1 AND expr2
expr1 ==> expr2
expr1 OR expr2
(expression)
Notation
F/R/W/A
PAB-1
PAB-2
Access
PAB-1
XAB1
PAB-2
R/W/A
XAB1
Fetch
Listing the Breakpoint Unit Triggers Available
*
*
*
*
Table 11-3. Notation used in Breakpoint Unit Triggering
Trigger 1 configured to look for match on the PAB bus. On 1st occurrence of a
match, the trigger is asserted.
Trigger 1 configured to look for match on the PAB bus. On Nth occurrence of a
match, the trigger is asserted, where N is the programmed 16-bit counter value.
Trigger 1 configured to look for match on the XAB1 bus. On 1st occurrence of a
match, the trigger is asserted.
Trigger 1 configured to look for match on the XAB1 bus. On Nth occurrence of a
match, the trigger is asserted, where N is the programmed 16-bit counter value.
Trigger 2 configured to look for match on the PAB bus. On 1st occurrence of a
match, the trigger is asserted.
Trigger 2 configured to look for match on the PAB bus. On Nth occurrence of a
match, the trigger is asserted, where N is the programmed 16-bit counter value.
Trigger 2 configured to look for an 8-bit, 16-bit, or 32-bit match on a data value
on the CDB bus. In addition, any bits in the value can be masked to look at only
a portion of the data value. On 1st occurrence of a match, the trigger is asserted.
The trigger is only asserted on instruction fetches from program memory. It is
not asserted if data is accessed from the program memory.
The trigger is only asserted on data accesses from memory. It is not asserted for
instruction fetches from the memory.
The trigger is asserted on any access to the memory — instruction fetch, data
read, write, or access.
The trigger is asserted on any data access to the memory — data read, write, or
access.
The trigger is asserted on the Nth occurrence of detecting the expression. This
is used when breakpoints are ORed or ANDed together.
The trigger is asserted when “expr1” occurs OR when “expr2” occurs. The
occurrence of either asserts the trigger.
The trigger is asserted when “expr1” occurs at the same time as when “expr2”
occurs. Both must occurrence for the trigger to be asserted. This is particularly
useful for examining a data value at a particular location in data memory.
“expr1” must first occur, followed by “expr2”. When this occurs, the condition
becomes true and the trigger is asserted.
DSP56800E Core Reference Manual
Description
Freescale Semiconductor