dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 175

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

5.5
Some algorithms require calculations that exceed the range or precision of the 16- and 32-bit operations
that the DSP56800E architecture supports. To assist in implementing these algorithms, the DSP56800E
provides several instructions targeted toward extended-precision and multi-precision calculations.
5.5.1
Two instructions, ADC and SBC, assist in performing extended-precision addition and subtraction.
Example 5-19 illustrates the use of the ADC instruction in 64-bit addition. Two 64-bit operands in memory
are summed, 32 bits at a time, with the carry out of the low-order addition added into the high-order
portion. The final sum is stored in both the A and B registers.
X:$103:X:$102:X:$101:X:$100 + X:$203:X:$202:X:$201:X:$200 = A2:A1:A0:B1:B0
Subtraction is carried out in a similar manner. As illustrated in Example 5-20, the low-order 32-bit
subtraction is performed first, with any borrow being reflected in the carry bit in the status register. The
high-order subtraction is then performed, with the borrow subtracted to achieve the correct result.
X:$103:X:$102:X:$101:X:$100 – X:$203:X:$202:X:$201:X:$200 = A2:A1:A0:B1:B0
5.5.2
Two instructions are provided to assist with multi-precision multiplications: MPYSU and MACSU. When
these instructions are used, the multiplier accepts one signed two’s-complement operand and one unsigned
two’s-complement operand.
Figure 5-20 on page 5-30 shows the process for multiplying a 16-bit value with a 32-bit value, resulting in
a 36-bit product. The 16-bit value is multiplied by each of the 16-bit halves of the larger value, and the
results are summed, with the second product offset by 16 bits so the products align properly.
Freescale Semiconductor
Extended- and Multi-Precision Operations
Extended-Precision Addition and Subtraction
Multi-Precision Fractional Multiplication
MOVE.L
MOVE.L
ADD
MOVE.L
MOVE.L
ADC
MOVE.L
MOVE.L
SUB
MOVE.L
MOVE.L
SBC
X:$100,B
X:$200,Y
Y,B
X:$102,A
X:$202,Y
Y,A
X:$100,B
X:$200,Y
Y,B
X:$102,A
X:$202,Y
Y,B
Example 5-20. 64-Bit Subtraction
Example 5-19. 64-Bit Addition
Data Arithmetic Logic Unit
; Get Operand1 (Lower 32 bits, sign ext)
; Get Operand2 (Lower 32 bits)
; First 32-bit addition,
; Get Operand1 (Upper 32 bits)
; Get Operand2 (Upper 32 bits)
; Second 32-bit addition
; Get Operand1 (Lower 32 bits, sign ext.)
; Get Operand2 (Lower 32 bits)
; First 32-bit subtraction
; Get Operand1 (Upper 32 bits)
; Get Operand2 (Upper 32 bits)
; Second 32-bit subtraction
Extended- and Multi-Precision Operations
5-29