dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 681

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

The condition code bits are updated automatically after each instruction is executed according to the rules
that are outlined in the following sections. Be careful when changing the values of the condition code bits
under program control, because the state of the condition code bits can affect the execution of subsequent
instructions.
B.2.1
The SZ bit is a latching bit (sticky bit) that indicates that word growth is occurring in an algorithm. It is set
when a 36-bit accumulator is written to data memory if bits 30 and 29 of the source accumulator that is
used in the move operation are not the same—that is, if both are not ones or zeros. SZ is not affected
otherwise.
The SZ bit is designed for use in the FFT algorithm. It indicates that the next pass in the algorithm should
scale its results before computation, allowing FFT data to be scaled only on passes where necessary, which
in turn helps guarantee maximum accuracy in an FFT calculation.
The exact algorithm for calculating SZ is:
The calculation of SZ is not affected by the condition code mode or by the operation of the MAC output
limiter. The SZ bit is latched once it is set, and it is cleared only by processor reset or by an instruction that
explicitly clears it.
B.2.2
The limit bit (L) is a latching bit (sticky bit) that indicates that overflow has occurred in a data ALU
operation or that limiting has occurred when one of the four accumulators (A, B, C, D) is moved with a
single move or through a parallel move.
L is not affected otherwise. The calculation of L is not directly affected by either the MAC output limiter
or the condition code mode. However, the MAC output limiter and the condition code mode do affect the
calculation of the overflow (V) bit, which may indirectly affect the calculation of L.
The TFR and TFRA instructions are register-to-register transfer instructions and are not considered
“move” instructions in the equation for calculating L. As a result, neither instruction will set the L bit, even
if saturation is enabled (SA = 1) and saturation occurs. Note that the TFR instruction can set the L bit if it
has a parallel move and if limiting occurs in that parallel move.
Freescale Semiconductor
Z
Bit 2
V
Bit 1
C
Bit 0
Name
1.For descriptions of bits 15–8 of the SR, see Table 8-2 on page 8-8.
SZ = SZ | (Bit 30 ⊕ Bit 29)
L = L | V | (limiting due to a move)
Size Bit (SZ)
Limit Bit (L)
Zero—Indicates whether result of last operation
was zero or not
Overflow—Indicates whether result of last oper-
ation overflowed its destination
Carry—Set if a carry out or borrow was gener-
ated in addition or subtraction
Table B-1. Condition Code Bit Descriptions
Description
Condition Code Calculation
0 = Result was non-zero.
1 = Result was zero.
0 = Did not overflow.
1 = Overflowed destination.
0 = No carry occurred during operation.
1 = Carry-out occurred during operation.
1
(Continued)
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