dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 523

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

MACR
Operation:
D + (S1 × S2) + r → D (no parallel move)
D + (S1 × S2) + r → D (one parallel move)
D + (S1 × S2) + r → D (two parallel reads)
Description: Multiply the two signed 16-bit source operands, add or subtract the 32-bit fractional product to or from
Usage:
Example:
Explanation of Example:
Freescale Semiconductor
Before Execution
A2
0
the third operand, and round and store the result in the destination (D). Both source operands must be
located in the FF1 portion of an accumulator or in X0, Y0, or Y1. The fractional product is first sign
extended before the 36-bit addition is performed, followed by the rounding operation. If the destination
is one of the 16-bit registers, it is first sign extended internally and concatenated with 16 zero bits to
form a 36-bit operand before being added to the fractional product. The addition is then followed by
the rounding operation, and the high-order 16 bits of the result are then stored. This instruction uses
the rounding technique that is selected by the R bit in the OMR. When the R bit is cleared (default
mode), convergent rounding is selected; when the R bit is set, two’s-complement rounding is selected.
Refer to Section 5.9, “Rounding,” on page 5-43 for more information about the rounding modes. Note
that the rounding operation always zeros the LSP of the result if the destination (D) is an accumulator
or the Y register.
This instruction is used for the multiplication, accumulation, and rounding of fractional data.
MACR
Prior to execution, the 16-bit X0 register contains the value $0280 (or fractional value 0.019531250),
the 16-bit Y0 register contains the value $0200 (or fractional value 0.015625), and the 36-bit A accu-
mulator contains the value $0:0000:8000 (or fractional value 0.000015259). Execution of the MACR
instruction multiplies the 16-bit signed value in the X0 register by the 16-bit signed value in Y0 (yield-
ing the fractional product result of $000A:0000 = 0.000305176), adds the resulting 32-bit product to
the 36-bit A accumulator ($0:000A:8000 = 0.00320435), rounds the result, and stores the rounded re-
sult ($0:000A:0000 = 0.000305176) back into the A accumulator. In parallel, X0 and Y0 are updated
with new values that are fetched from the data memory, and the two address registers (R0 and R3) are
post-incremented by one. In this example, the default rounding technique (convergent rounding) is per-
formed (bit R in the OMR is cleared). If two’s-complement rounding is utilized (R bit is set), the result
in accumulator A is $0:000B:0000 = 0.000335693.
FF00
0000
A1
Y1
Y0,X0,A
X0
SR
Multiply-Accumulate and Round
X:(R0)+,Y0
8000
0200
0280
0300
A0
Y0
Instruction Set Details
Assembler Syntax:
MACR
MACR
MACR
X:(R3)+,X0 ; multiply-accumulate
After Execution
A2
0
(+)S1,S2,D
S1,S2,D
S1,S2,D
000A
FF00
; fractional with rounding
A1
Y1
SR
X0
(no parallel move)
(one parallel move)
(two parallel reads)
0000
0300
0288
0310
A0
Y0
MACR
A-179