dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 342

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

JTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
The TAP controller provides access to the IR through the core JTAG port. The other core JTAG registers
must be individually selected by the IR.
11.5.2.4
The TAP controller is a sixteen state synchronous finite state machine, used to sequence the core JTAG
port through its valid operations:
The TAP controller is shown in Figure 11-17. The TAP controller will asynchronously be reset to the
Test-Logic-Reset state upon assertion low of tlm_res_b pin. When the tlm_res_b signal is deasserted and
the core_tap_en pin is asserted, the TAP controller responds to changes of the TMS and TCK signals.
Transitions from one state to another occur on the rising edge of TCK. The value shown adjacent to each
state transition in this figure represents the signal present at TMS at the time of a rising edge of TCK.
11-30
CORE_TDI
CORE_TLM_SEL
•
•
•
•
CORE_TAP_EN
TLM_RESET_B
Serially shift in or out a core JTAG instruction
Update (and decode) the core JTAG Instruction Register
Serially output the core ID code
Serially shift in or out and update the EOnCE registers.
Core TAP Controller
TMS
TCK
The core JTAG port oversees the shifting of data into and out of the
EOnCE port through the CORE_TDI and CORE_TDO pins, respectively.
The shifting, in this case, is guided by the same tap controller used when
shifting core JTAG Instruction Register (IR) information.
Core Bypass Register
Instruction Register
Core ID Register
Figure 11-16. Core JTAG Block Diagram
DSP56800E Core Reference Manual
Decode
Controller
TAP
NOTE:
From EOnCE Port
To EOnCE Port
Freescale Semiconductor
CORE_TDO