dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 563

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

MPYR
Operation:
+ S1 × S2 + r → D
S1 × S2 + r → D
S1 × S2 + r → D
Description: Multiply the two signed 16-bit source operands, round the 32-bit fractional product, and place the re-
Usage:
Example:
Explanation of Example:
Freescale Semiconductor
Before Execution
A2
0
sult in the destination (D). Both source operands must be located in the FF1 portion of an accumulator
or in X0, Y0, or Y1. The fractional product is sign extended before the rounding operation, and the
result is then stored in the destination. If the destination is one of the 16-bit registers, only the high-or-
der 16 bits of the rounded fractional result are stored. This instruction uses the rounding technique that
is selected by the R bit in the OMR. When the R bit is cleared (default mode), convergent rounding is
selected; when the R bit is set, two’s-complement rounding is selected. Refer to Section 5.9, “Round-
ing,” on page 5-43 for more information about the rounding modes. Note that the rounding operation
will always zero the LSP of the result if the destination (D) is an accumulator or the Y register.
This instruction is used for the multiplication and rounding of fractional data.
MPYR
Prior to execution, the 16-bit X0 register contains the value $02A0 (or fractional value 0.020507813),
and the 16-bit Y0 register contains the value $0200 (or fractional value 0.015625). The contents of the
destination register are not important prior to execution because they have no effect on the calculated
value. Execution of the MPYR instruction multiplies the 16-bit signed value in the X0 register by the
16-bit signed value in Y0 (yielding the fractional product result of $000A:8000 = 0.000320435),
rounds the result, and stores the rounded result ($0:000A:0000 = 0.000305176) back into the A accu-
mulator. In parallel, X0 and Y0 are updated with new values that are fetched from the data memory,
and the two address registers (R0 and R3) are post-incremented by one. In this example, the default
rounding technique (convergent rounding) is performed (bit R in the OMR is cleared). If two’s-com-
plement rounding is utilized (R bit is set), the result in accumulator A is $0:000B:0000 = 0.000335693.
(no parallel move)
(one parallel move)
(two parallel reads)
FF00
1000
A1
Y1
Y0,X0,A
SR
X0
Signed Multiply and Round
X:(R0)+,Y0
02A0
1234
0200
0300
A0
Y0
Instruction Set Details
Assembler Syntax:
MPYR
MPYR
MPYR
X:(R3)+,X0
After Execution
A2
0
(+)S1,S2,D
S1,S2,D
S1,S2,D
000A
FF00
; multiply fractional
; signed and round
A1
Y1
SR
X0
(no parallel move)
(one parallel move)
(two parallel reads)
0000
0300
0288
0310
A0
Y0
MPYR
A-219