dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 55

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

3.2
The DSP56800E architecture supports byte (8-bit), word (16-bit), and long-word (32-bit) integer data
types. It also supports word, long-word, and accumulator (36-bit) fractional data types.
Fractional and integer representations differ in the location of the decimal (or binary) point. For fractional
arithmetic, the decimal (or binary) point is always located immediately to the right of the MSP’s most
significant bit. For integer values, the decimal is always located immediately to the right of the value’s
least significant bit. Table 3-2 on page 3-7 shows the location of the decimal point (binary point), bit
weightings, and operand alignment for different fractional and integer representations.
The interpretation of a data value (fractional or integer) is determined by the instruction that uses it. In
some cases, the same instruction can operate on both types of data, with identical results. In others,
different instructions are used for processing fractional numbers and integer numbers. Multiplication, for
example, is performed with the MPY instruction for fractional values and with IMPY.L for integer values.
The following subsections describe the DSP56800E data types and their interpretation.
Freescale Semiconductor
Controller
Program
Unit
DSP56800E Data Types
Name
HWS
FIRA
FISR
OMR
LC2
LA2
PC
SR
LA
LC
(Bits)
Size
21
24
24
24
21
13
16
16
16
16
Table 3-1. DSP56800E Core Registers (Continued)
Program counter—Composed of a dedicated 16-bit register (bits 15-0 of the pro-
gram counter) as well as 5 bits stored in the upper byte of the status register.
Loop address—Contains address of the last instruction word in a hardware DO
loop.
Loop address 2—Saves loop address for outer loop.
Hardware stack—Provides access to the hardware stack as a two-location LIFO
buffer.
Fast interrupt return address—Saves a 21-bit copy of the return address upon
entering a level 2 fast interrupt service routine.
Fast interrupt status register—Saves a copy of the condition code register, the
stack alignment state, and the hardware looping status upon entering a level 2
fast interrupt service routine.
Operating mode register—Sets up modes for the core.
Status register—Contains status, control, and the 5 MSBs of the program counter
register.
Loop counter—Contains loop count when hardware looping.
Loop counter 2—Saves loop count for outer loop.
Data Types and Addressing Modes
Description
DSP56800E Data Types
3-5