dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 377

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ANDC
Operation:
#xxxx • D → D
#xxxx • X:<ea> → X:<ea> (no parallel move)
where • denotes the logical AND operator
Implementation Note:
Description: Perform a logical AND operation on a 16-bit immediate data value with the destination operand, and
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Instruction Fields:
Freescale Semiconductor
This instruction is implemented by the assembler as an alias to the BFCLR instruction, with the 16-bit
immediate value inverted (one’s-complement) and used as the bit mask. It will dis-assemble as a
BFCLR instruction.
store the results back into the destination. C is also modified as described in “Condition Codes Affect-
ed.” This instruction performs a read-modify-write operation on the destination and requires two des-
tination accesses.
ANDC
Prior to execution, the 16-bit X memory location X:$5000 contains the value $FFFF. Execution of the
instruction performs a logical AND operation on the 16-bit value in X:$5000 (that is, $FFFF) and the
mask value $0055 and stores the result in X:$5000. The C bit is set because all of the bits selected by
the inverted value of the mask are set.
For destination operand SR:
For other destination operands:
L
C
If all bits in the mask are set, the instruction executes two NOPs and sets the C bit.
Refer to the section on the BFCLR instruction for legal operand and timing information.
Before Execution
X:$5000
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the one’s-complement of the mask are set
(no parallel move)
SR
P4
14
For this destination only, the C bit is not updated as is done for all other destination operands.
All SR bits except bits 14–10 are updated with values from the bitfield unit.
Bits 14–10 of the mask operand must be set.
Cleared if at least 1 bit specified by the one’s-complement of the mask is not set
#$0055,X:$5000
13
P3
P2
12
FFFF
0300
MR
Logical AND Immediate
P1
11
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
ANDC
ANDC
I0
8
; AND with immediate data
SZ
7
6
L
5
E
After Execution
X:$5000
#iiii,D (no parallel move)
#iiii,X:<ea>(no parallel move)
U
4
CCR
SR
N
3
2
Z
0055
0301
V
1
C
0
ANDC
A-33