MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 93

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the FxCDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FxCDIV
register has not been written since the last reset. If the FxCDIV register has not been written to, the flash
command loaded during a command write sequence will not execute and FxSTAT[FACCERR] will be set.
Freescale Semiconductor
Program and erase command execution time will increase proportionally
with the period of FCLK. Programming or erasing the flash memory with
FCLK < 150 kHz must be avoided. Setting FxCDIV to a value such that
FCLK < 150 kHz can destroy the flash memory due to overstress. Setting
FxCDIV to a value such that FCLK > 200 kHz can result in incomplete
programming or erasure of the flash memory cells.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 3-9. Determination Procedure for PRDIV8 and FDIV Bits
set FDIV[5:0] = PRDCLK[kHz]/200-1
FCLK = (PRDCLK)/(1+FDIV[5:0])
PRDCLK = bus_clock/8
PRDIV8 = 0 (reset)
PRDCLK[kHz]/200
set PRDIV8 = 1
bus_clock
an integer?
≥12.8MHz?
bus_clock
START
0.3MHz?
END
no
yes
yes
CAUTION
yes
no
no
PRDCLK = bus_clock
set FDIV[5:0] = INT(PRDCLK[kHz]/200)
ALL PROGRAM AND ERASE
COMMANDS IMPOSSIBLE
Memory
3-37