MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 626

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.4.3.4
This section specifies the ColdFire processor and debug module’s generation of the processor status (PST)
and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an
instruction is defined as follows:
where the {...} definition is optional operand information defined by the setting of the CSR, and [...]
indicates the presence of one value from the list.
The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST
value {0x08, 0x09, or 0x0B} identifies the size and presence of valid data to follow in the PST trace buffer
(PSTB) {1, 2, or 4 bytes, respectively}. Additionally, CSR[DDC] specifies whether operand data capture
is enabled and what size. Also, for certain change-of-flow instructions, CSR[BTB] provides the capability
to display the target instruction address in the PSTB (2 or 3 bytes) using a PST value of 0x0D or 0x0E,
respectively.
26.4.3.4.1
Table 26-27
register. In this definition, the y suffix generally denotes the source, and x denotes the destination operand.
For a given instruction, the optional operand data is displayed only for those effective addresses
referencing memory. The DD nomenclature refers to the DDATA outputs.
26-62
add.l
add.l
adda.l
addi.l
addq.l
addx.l
and.l
and.l
andi.l
asl.l
asr.l
bcc.{b,w,l}
bchg.{b,l}
bchg.{b,l}
bclr.{b,l}
Instruction
PST = 0x01, {PST = 0x0[89B], DDATA = operand}
shows the PST/DDATA specification for user-mode instructions. Rn represents any {Dn, An}
Processor Status, Debug Data Definition
User Instruction Set
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
<ea>y,Dx
Dy,<ea>x
#<data>,Dx
Dy,Dx
<ea>y,Dx
Dy,<ea>x
#<data>,Dx
{Dy,#<data>},Dx
{Dy,#<data>},Dx
#<data>,<ea>x
Dy,<ea>x
#<data>,<ea>x
<ea>y,Ax
#<data>,<ea>x
Operand Syntax
Table 26-27. PST/DDATA Specification for User-Mode Instructions
PST = 0x01, {PST = 0x0B, DD = source operand}
PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination}
PST = 0x01, {PST = 0x0B, DD = source operand}
PST = 0x01
PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination}
PST = 0x01
PST = 0x01, {PST = 0x0B, DD = source operand}
PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination}
PST = 0x01
PST = 0x01
PST = 0x01
if taken, then PST = 0x05, else PST = 0x01
PST = 0x01, {PST = 0x08, DD = source}, {PST = 0x08, DD = destination}
PST = 0x01, {PST = 0x08, DD = source}, {PST = 0x08, DD = destination}
PST = 0x01, {PST = 0x08, DD = source}, {PST = 0x08, DD = destination}
PST/DDATA
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